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2019 IEEE 13th International Conference on ASIC (ASICON)最新文献

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A FT Trimming Circuit Based on EPROM and Pin Multiplexing 一种基于EPROM和引脚复用的FT微调电路
2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/ASICON47005.2019.8983451
Yan-Ming Li, Xiao-Xiao Wang, Xiao-Li Xi, Jian Sun, Zhong-Hui Chen
{"title":"A FT Trimming Circuit Based on EPROM and Pin Multiplexing","authors":"Yan-Ming Li, Xiao-Xiao Wang, Xiao-Li Xi, Jian Sun, Zhong-Hui Chen","doi":"10.1109/ASICON47005.2019.8983451","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983451","url":null,"abstract":"A Final Test (FT) trimming circuit with 4x8 bit single-layer polysilicon EPROM and Pin multiplexing is presented in this paper. The main part of the proposed circuit consists of Pin multiplexing circuit, power circuit of IP core, IIC logic and EPROM. The one-time programmable IP core is designed and implemented by IIC bus drive technology and FT trimming technology so as to achieve chip trimming and functional mode differentiation. The trimming circuit can effectively increase the programmability of the chip so as to reduce the influence of process offset and fluctuation, improving the yield and reliability of the chip. The proposed circuit has been successfully applied to a Li-ion battery protection integrated circuits (ICs) with a 0.18μ $m$ BCD process. The experimental results verify the reliability of the circuit and meet the performance requirements of circuit design.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124619388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
SVM Based Network Intrusion Detection for the UNSW-NB15 Dataset 基于SVM的UNSW-NB15数据集网络入侵检测
2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/ASICON47005.2019.8983598
Dishan Jing, Hai-Bao Chen
{"title":"SVM Based Network Intrusion Detection for the UNSW-NB15 Dataset","authors":"Dishan Jing, Hai-Bao Chen","doi":"10.1109/ASICON47005.2019.8983598","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983598","url":null,"abstract":"Due to the growth of internet security issues, Network Intrusion Detection System (NIDS) becomes an integral part of the IoT environment. In the past, most research on intrusion detection was experimented with the KDDCUP99 dataset. However, the KDDCUP99 dataset lacks some typical examples when evaluating NIDS compared with the UNSW-NB15 dataset. In this paper, we propose Support Vector Machine (SVM) with a new scaling method for binary-classification and multi-classification experiments. The performance of our method is evaluated through accuracy, detection rate and false positive rate. Compared with other methods, the superiority of the proposed SVM method is shown by the experimental results. The accuracy of the proposed method reaches 85.99% for binary-classification, compared to 78.47% by Expectation-Maximization (EM) clustering. For multi-classification, the proposed SVM method can achieve the testing accuracy of 75.77%, which is 6.17% higher than that of Naïve Bayes (NB).","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129837732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 53
A SAR-Assisted Continuous-Time Incremental ΣΔ ADC With First-Order Noise Coupling 具有一阶噪声耦合的sar辅助连续时间增量ΣΔ ADC
2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/ASICON47005.2019.8983671
Yu-Lun Hsieh, Tai-Cheng Lee
{"title":"A SAR-Assisted Continuous-Time Incremental ΣΔ ADC With First-Order Noise Coupling","authors":"Yu-Lun Hsieh, Tai-Cheng Lee","doi":"10.1109/ASICON47005.2019.8983671","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983671","url":null,"abstract":"A 25-kHz 3rd-order continuous-time incremental sigma-delta modulator is proposed by utilizing a 5-bit successive-approximation-register (SAR) quantizer, incorporating 1st-order noise coupling (NC) and excess-loop-delay compensation (ELDC) into the switched-capacitor (SC) SAR digital-to-analog converter (DAC). This prototype fabricated in a TSMC 40 nm LP CMOS technology measures a peak 71.98 dB SNDR at an over-sampling ratio (OSR) of 32, yielding a Schreier FoM of 160.5 dB and a Walden FoM of 1.39 p.J/conversion-step. The modulator occupies an active area smaller than 0.32 mm2 and consumes 225 μW.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130320628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of Current-Assisted Photonic Demodulator (CAPD) for Time-of-Flight CMOS Image Sensor 用于飞行时间CMOS图像传感器的电流辅助光子解调器设计
2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/asicon47005.2019.8983514
Cristine Jin Estrada, Chen Xu, M. Chan
{"title":"Design of Current-Assisted Photonic Demodulator (CAPD) for Time-of-Flight CMOS Image Sensor","authors":"Cristine Jin Estrada, Chen Xu, M. Chan","doi":"10.1109/asicon47005.2019.8983514","DOIUrl":"https://doi.org/10.1109/asicon47005.2019.8983514","url":null,"abstract":"This paper presents an overview of 3D real-time imaging system using electro-optical demodulator technique. The general principle to convert the phase difference between the emitted and received signals to the distance between the object and the camera is first explained, followed by the derivation of the demodulation scheme. The function of the photonic mixer device (PMD) in the scheme will be explained. In particular, the design tradeoffs of the widely popular Current-Assisted Photonic Demodulator (CAPD) will be described based on a newly developed physical model.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"2005 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123910244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Radiation Hardened Clock Inverter Cell with High Reliability for Mitigating SET in Clock Network 一种用于时钟网络中抑制SET的高可靠性抗辐射时钟逆变单元
2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/ASICON47005.2019.8983515
Jie Li, Liyi Xiao, Hongchen Li, Lulu Liao, Chenxu Wang
{"title":"A Radiation Hardened Clock Inverter Cell with High Reliability for Mitigating SET in Clock Network","authors":"Jie Li, Liyi Xiao, Hongchen Li, Lulu Liao, Chenxu Wang","doi":"10.1109/ASICON47005.2019.8983515","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983515","url":null,"abstract":"With the technology node scaling down, clock network is becoming more and more vulnerable to SET. In this paper, a radiation hardened clock inverter cell is proposed for mitigating SET in the clock network. Theoretical analysis and simulation results show that the proposed cell can efficiently mask the SET pulse propagating in the clock network. And also, the proposed cell can solve the problem that a short path exists between power supply and ground when the cell is affected by SET. This avoids the critical threaten of the strong current on the circuit.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123378532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Buffer Sizing for Near-Threshold Clock Tree using Improved Genetic Algorithm 基于改进遗传算法的近阈值时钟树缓冲大小
2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/ASICON47005.2019.8983483
Yiran Sun, Ju Zhou, Shiying Zhang, Xuexiang Wang
{"title":"Buffer Sizing for Near-Threshold Clock Tree using Improved Genetic Algorithm","authors":"Yiran Sun, Ju Zhou, Shiying Zhang, Xuexiang Wang","doi":"10.1109/ASICON47005.2019.8983483","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983483","url":null,"abstract":"Comparing with super-threshold designs, clock tree design in near-threshold voltage (NTV) region is more susceptive to signal slew, and timing violations occur much more often due to slew degradation at sink nodes and difference among sink nodes. However, when optimizing clock tree in super-threshold region, signal slew is merely considered as transition constraint with an upper bound. Little concern is taken about slew at sink nodes, which is particularly important in NTV region and system performance would be badly weakened if it is not controlled properly. Here, we propose an innovative formulation for optimization of buffer size in near-threshold clock tree using improved genetic algorithm combined with non-linear programming. With slew at sink nodes considered, we are able to minimize a combination of skew, slew and area cost. On average, skew is improved by 23.8%, and max slew at sink nodes and slew difference among sink nodes are reduced by 24.6% and 47.8% separately. At the same time, area cost of buffer is also reduced by 8.5%. The optimal solution can set as buffer sizes directly without any subsequent discretization procedure.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123628115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A GaSb/In0.4Ga0.6As Heterojunction Z-Shaped Tunnel Field-Effect Transistor with High Performance 一种高性能GaSb/In0.4Ga0.6As异质结z形隧道场效应晶体管
2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/ASICON47005.2019.8983662
Jiarui Bao, Shuyan Hu, Guangxi Hu, Laigui Hu, Ran Liu, Lirong Zheng
{"title":"A GaSb/In0.4Ga0.6As Heterojunction Z-Shaped Tunnel Field-Effect Transistor with High Performance","authors":"Jiarui Bao, Shuyan Hu, Guangxi Hu, Laigui Hu, Ran Liu, Lirong Zheng","doi":"10.1109/ASICON47005.2019.8983662","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983662","url":null,"abstract":"A GaSb/ln<inf>0.4</inf>Ga<inf>0.6</inf>As heterojunction Z-Shaped TFET is proposed and investigated by a TCAD simulation tool. A low subthreshold swing (16.2 mV/dec) is obtained. A large on- state current, I<inf>on</inf>(748μA/μm) and a large on-and off-state current ratio, <tex>$I$</tex><inf>on</inf>/I<inf>off</inf> (7.48 x10<sup>9</sup>) are achieved for the device under a drain bias of 0.5 V. In addition, the temperature dependence of the proposed device is presented, and it shows that low temperatures favor for <tex>$I$</tex><inf>on</inf>/I<inf>off</inf>. It is also revealed that the on-state current can be enhanced by adjusting the device geometry. Moreover, the device can work at a low supply voltage (~0.2 V).","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121431277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Synergistic Effect of BTI and Process Variations on Impact and Monitoring of Combination Circuit BTI和工艺变化对组合电路冲击和监测的协同效应
2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/asicon47005.2019.8983690
Linzhe Li, Liyi Xiao, Jie Li, He Liu, Zhigang Mao
{"title":"Synergistic Effect of BTI and Process Variations on Impact and Monitoring of Combination Circuit","authors":"Linzhe Li, Liyi Xiao, Jie Li, He Liu, Zhigang Mao","doi":"10.1109/asicon47005.2019.8983690","DOIUrl":"https://doi.org/10.1109/asicon47005.2019.8983690","url":null,"abstract":"With the technology node scaling down, aging effect and process variations have become the most critical reliability issues for integrated circuit. In this paper, the influence of BTI effect and process variation on threshold voltage is analyzed. Then, the delay of logic gate and the change of subthreshold current are deduced from the change of threshold voltage. Finally, the logic gate and ISCAS85 circuit are simulated by HSPICE in PTM 45nm model. Simulation results show the relationship between delay and subthreshold current with aging time, which can be used to predict the degradation of circuit parameters. The change of circuit delay can be quickly monitored by measuring subthreshold current.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114565471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Nonvolatile Binary CNN Accelerator with Extremely Low Standby Power using RRAM for IoT Applications 非易失性二进制CNN加速器，待机功耗极低，使用RRAM用于物联网应用
2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/ASICON47005.2019.8983658
Yujie Cai, Keji Zhou, X. Xue, Mingyu Wang, Xiaoyang Zeng
{"title":"Nonvolatile Binary CNN Accelerator with Extremely Low Standby Power using RRAM for IoT Applications","authors":"Yujie Cai, Keji Zhou, X. Xue, Mingyu Wang, Xiaoyang Zeng","doi":"10.1109/ASICON47005.2019.8983658","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983658","url":null,"abstract":"Recently, with the development of 5G communications technology, a fully interconnected world is coming. Because 5G has the characteristics of low power consumption, high speed, low cost and small delay, the change brought to the Internet of Things industry is dramatic [1]. Artificial intelligence technology has great potential in the field of IoT devices, but the huge computational complexity makes it difficult to be realized on a power-critical device. In this paper, we demonstrate a nonvolatile binary convolutional neural network accelerator. The main contributions of this work are summarized as follows: (1) A nonvolatile binary CNN data path based on RRAM, which can be fully power-gated in standby state; (2) The matrix multiplication and addition is performed by RRAM other than digital logic, with the binary weights stored in the RRAM; (3) Since the accelerator can be fully powered down, the power dissipated during the standby state is almost zero.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116205419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Novel smart card SoC memory architecture based on embedded STT-MRAM 基于嵌入式STT-MRAM的新型智能卡SoC存储器结构
2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/ASICON47005.2019.8983653
Kaiwen Lu, Feng Yan, Xingjie Liu, Dongsheng Liu, Peng Liu, Bo Liu
{"title":"Novel smart card SoC memory architecture based on embedded STT-MRAM","authors":"Kaiwen Lu, Feng Yan, Xingjie Liu, Dongsheng Liu, Peng Liu, Bo Liu","doi":"10.1109/ASICON47005.2019.8983653","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983653","url":null,"abstract":"In the applications of Internet of Things (IoT), the limitations of the common NVM + RAM hybrid memory architecture cannot simultaneously provided the solution of lower power, low resource consumption and nonvolatile which are critical for IoT designing. Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) has become a major candidate for on-chip memory because of its ideal memory characteristics, such as nonvolatile, near zero standby leakage power and compatibility with CMOS. Therefore, this paper focuses on the application of STT-MRAM in the storage of IoT. We design the eSTT-MRAM non-hybrid memory architecture for smart card SoCs. The prototype verification results on Xilinx's ARTIX-7 XC7A100T FPGA platform show that the STT-MRAM-based memory architecture can greatly improve the operating efficiency of SoC programs and reduce the dynamic power consumption of the system due to data storage.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"154 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116374183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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