Buffer Sizing for Near-Threshold Clock Tree using Improved Genetic Algorithm

Abstract

Comparing with super-threshold designs, clock tree design in near-threshold voltage (NTV) region is more susceptive to signal slew, and timing violations occur much more often due to slew degradation at sink nodes and difference among sink nodes. However, when optimizing clock tree in super-threshold region, signal slew is merely considered as transition constraint with an upper bound. Little concern is taken about slew at sink nodes, which is particularly important in NTV region and system performance would be badly weakened if it is not controlled properly. Here, we propose an innovative formulation for optimization of buffer size in near-threshold clock tree using improved genetic algorithm combined with non-linear programming. With slew at sink nodes considered, we are able to minimize a combination of skew, slew and area cost. On average, skew is improved by 23.8%, and max slew at sink nodes and slew difference among sink nodes are reduced by 24.6% and 47.8% separately. At the same time, area cost of buffer is also reduced by 8.5%. The optimal solution can set as buffer sizes directly without any subsequent discretization procedure.