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2019 IEEE 13th International Conference on ASIC (ASICON)最新文献

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A35.2 dBm CMOS RF Power Amplifier Using an 8-Way Current-Voltage Combining Transformer with Harmonic Control 采用8路流压组合变压器和谐波控制的35.2 dBm CMOS射频功率放大器
2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/ASICON47005.2019.8983512
Hejia Cai, Yan Hu, Zhiliang Hong
{"title":"A35.2 dBm CMOS RF Power Amplifier Using an 8-Way Current-Voltage Combining Transformer with Harmonic Control","authors":"Hejia Cai, Yan Hu, Zhiliang Hong","doi":"10.1109/ASICON47005.2019.8983512","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983512","url":null,"abstract":"A fully integrated CMOS power amplifier with 8-way current-voltage combining transformer is performed in tsmc65nm GP CMOS process. For the high power CMOS PA design, a novel hybrid-type power combining transformer is proposed. Four identical PAs are used and their output power are combined by an 8-way current-voltage combining transformer. With 3.3V power supply, the proposed power amplifier provides maximum output power of 35.2dBm and peak power added efficiency of 38.73% at 2.4GHz operating frequency. At 1dB compression point, the proposed power amplifier exhibits high output power of 33.1dBm with power add efficiency of 28.8%.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124409728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An Efficient Accelerator for Sparse Convolutional Neural Networks 稀疏卷积神经网络的高效加速器
2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/ASICON47005.2019.8983560
Weijie You, Chang Wu
{"title":"An Efficient Accelerator for Sparse Convolutional Neural Networks","authors":"Weijie You, Chang Wu","doi":"10.1109/ASICON47005.2019.8983560","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983560","url":null,"abstract":"In this paper, we propose a sparse convolutional neural network accelerator design on FPGAs. Similar to the DNNWEAVER architecture, our accelerator uses two-level hierarchy: multiple Processing Units (PUs) and each PU comprises a set of Processing Elements (PEs). To address the irregularity of sparse neural networks, we introduce a novel sparse dataflow for sparse CNN computing as well as weight merging method to balance the computation load on different PUs for better overall efficiency. We implement our design with 32 PUs and 14 PEs in each PU. When compared with DNNWEAVER on VGG16 network, our accelerator achieves 3.49x speedup and 3.05x energy saving on average when running at 150MHz on a Xilinx ZC706 board and reaches the speed of 400 GOPS.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127366353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Switching of 3300V Scaled IGBT by 5V Gate Drive 5V栅极驱动开关3300V缩放IGBT
2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/asicon47005.2019.8983633
T. Hiramoto, K. Satoh, T. Matsudai, W. Saito, K. Kakushima, T. Hoshii, K. Furukawa, M. Watanabe, N. Shigyo, H. Wakabayashi, K. Tsutsui, H. Iwai, A. Ogura, S. Nishizawa, I. Omura, H. Ohashi, K. Itou, T. Takakura, M. Fukui, S. Suzuki, K. Takeuchi, M. Tsukuda, Y. Numasawa
{"title":"Switching of 3300V Scaled IGBT by 5V Gate Drive","authors":"T. Hiramoto, K. Satoh, T. Matsudai, W. Saito, K. Kakushima, T. Hoshii, K. Furukawa, M. Watanabe, N. Shigyo, H. Wakabayashi, K. Tsutsui, H. Iwai, A. Ogura, S. Nishizawa, I. Omura, H. Ohashi, K. Itou, T. Takakura, M. Fukui, S. Suzuki, K. Takeuchi, M. Tsukuda, Y. Numasawa","doi":"10.1109/asicon47005.2019.8983633","DOIUrl":"https://doi.org/10.1109/asicon47005.2019.8983633","url":null,"abstract":"In this work, the switching of 3300V IGBTs by 5V gate drive voltage has been successfully demonstrated for the first time. IGBT was designed based on a scaling principle. Comparing with conventional 15V-driven non-scaled IGBTs, the tum-off tail current of the scaled devices significantly decreased. The improvement of $E_{mathrm{off}}$ vs $V_{mathrm{cesat}}$ relationship by 35% was achieved.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125009888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Minimum Output Ripple and Fixed Operating Frequency Based on Modulation Injection for COT Ripple Control Converter 基于调制注入的COT纹波控制变换器最小输出纹波和固定工作频率
2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/asicon47005.2019.8983591
MinhTri Tran, Yifei Sun, Y. Kobori, A. Kuwana, Haruo Kobayashi
{"title":"Minimum Output Ripple and Fixed Operating Frequency Based on Modulation Injection for COT Ripple Control Converter","authors":"MinhTri Tran, Yifei Sun, Y. Kobori, A. Kuwana, Haruo Kobayashi","doi":"10.1109/asicon47005.2019.8983591","DOIUrl":"https://doi.org/10.1109/asicon47005.2019.8983591","url":null,"abstract":"This paper proposes a minimum output ripple and fixed operating frequency technique based on the modulation injection for a constant on-time (COT) ripple control converter. Basically, the modulation injection approach aims to add a modulation signal to the output inductor to fix the operating frequency on the discontinuous conduction mode (DCM) and does not affect the inductor current ripple injection. Moreover, the spread spectrum of pulse width modulation (PWM) method is also applied to reduce the electromagnetic interference (EMI) noise. The illustrative simulation results indicate that the proposed converter operates stably at a fixed switching frequency (1.6MHz), and the output ripple is kept very small (5mVpp). EMI noise levels are also kept below 50mV, which is compared to 5V desired voltage.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"400 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123252164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Sampling Rate Enhancement for SAR-ADCs Using Adaptive Reset Approach for FOG Systems 利用自适应复位方法提高FOG系统sar - adc的采样率
2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/ASICON47005.2019.8983562
Chun-Ting Chen, Tsung-Yi Tsai, Y. Chiu, Chua-Chin Wang
{"title":"Sampling Rate Enhancement for SAR-ADCs Using Adaptive Reset Approach for FOG Systems","authors":"Chun-Ting Chen, Tsung-Yi Tsai, Y. Chiu, Chua-Chin Wang","doi":"10.1109/ASICON47005.2019.8983562","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983562","url":null,"abstract":"In this investigation, an adaptive reset strategy of a 10-bit SAR-ADC particularly designed for the applications in FOG (fiber optic gyroscope) systems is demonstrated with TSMC 40 nm CMOS technology. The proposed adaptive reset approach takes advantage of high correlation of the phase shift generated by continuous FOG signals such that MSB bits of two consecutive samples likely remain the same, which implies there is no need to re-converted. By replacing conventional all-reset method with the adaptive-reset strategy, the throughput of the SAR ADC is theoretically increased up to around 100%. The sampling rate is increased by 2 times compared with the conventional counterpart.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123786867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
3D Vertical RRAM Array and Device Co-design with Physics-based Spice Model 基于物理的Spice模型的3D垂直RRAM阵列和器件协同设计
2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/ASICON47005.2019.8983496
Weiiie Xu, Yudi Zhao, Peng Huang, Xiaoyan Liu, Jinfeng Kang
{"title":"3D Vertical RRAM Array and Device Co-design with Physics-based Spice Model","authors":"Weiiie Xu, Yudi Zhao, Peng Huang, Xiaoyan Liu, Jinfeng Kang","doi":"10.1109/ASICON47005.2019.8983496","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983496","url":null,"abstract":"This paper demonstrates the co-design of three-dimension (3D) Vertical Resistive Random Access Memory (RRAM) and the RRAM device. It presents a design consideration of 3D Vertical RRAM array in terms of array performance from the device point of view. A physics-based RRAM Spice model is used to evaluate the performance of 3D RRAM array, including write access voltage, read margin, energy consumption and switching speed. The effects of device parameters, device parasitic capacitance, device variation and the 3D array size are discussed for design consideration. The simulation results show that with carefully choosing the RRAM device material and structure, a fast-switching, low energy consumption 3D RRAM array can be realized.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126733379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Precise Block-Based Statistical Timing Analysis with MAX Approximation Using Multivariate Adaptive Regression Splines 基于多元自适应样条回归的MAX逼近精确分块统计时序分析
2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/ASICON47005.2019.8983666
Leilei Jin, Wenjie Fu, Yu Zheng, Hao Yan
{"title":"A Precise Block-Based Statistical Timing Analysis with MAX Approximation Using Multivariate Adaptive Regression Splines","authors":"Leilei Jin, Wenjie Fu, Yu Zheng, Hao Yan","doi":"10.1109/ASICON47005.2019.8983666","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983666","url":null,"abstract":"The impact of process variations on timing has become significant in advanced technology nodes. In this paper, a multivariate adaptive regression splines (MARS) delay model is proposed that considers both global and local process variations to characterize this impact more accurately. In order to obtain MAX operation results, the first three moments of MARS gate delay distribution are calculated, converting the timing distribution to a skew-normal representation. Eventually, based on an approximation MAX operation, the block-based SSTA propagates the arrival time through the timing diagram. Tested with 10 ISCAS85 benchmark circuits, the average mean squared error and standard deviation error of the path delay calculation are 0.52% and 0.88%.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122878837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Improved Discrete Wavelet Analysis and Principal Component Analysis for EEG Signal Processing 改进的离散小波分析和主成分分析在脑电信号处理中的应用
2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/ASICON47005.2019.8983523
Yi-Hsiang Chen, Xiaoxin Cui, Kanglin Xiao, Dunshan Yu
{"title":"Improved Discrete Wavelet Analysis and Principal Component Analysis for EEG Signal Processing","authors":"Yi-Hsiang Chen, Xiaoxin Cui, Kanglin Xiao, Dunshan Yu","doi":"10.1109/ASICON47005.2019.8983523","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983523","url":null,"abstract":"Electroencephalogram (EEG) has significant applications on medical diagnosis and Brain Computer Interface (BCI). But the main obstacle of analyzing EEG signal is various types of noises to get actual information. Extracting important features is a key issue in this study. This paper uses the BCI Competition IV 2b motion imagery data, in which we provide a review of various prior art to determine the motion imaginary MI mission. Using machine learning to identify two different movements in the EEG signal, the data from nine subjects were analyzed by principal component analysis (PCA) combined with discrete wavelet (DWT) packet analysis. The extracted DWT feature is input into the support vector machine (SVM) classifier, and the experimental results shows that this method is better than traditional methods with a classification accuracy rate of 86.7%.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129921938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Low-power High-reliability STT-MRAM Write Scheme with Real-time Voltage Sensing Module 具有实时电压传感模块的低功耗高可靠性STT-MRAM写入方案
2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/ASICON47005.2019.8983459
Hao Li, Hongmei Yu, Dongsheng Liu, Peng Liu, Bo Liu
{"title":"A Low-power High-reliability STT-MRAM Write Scheme with Real-time Voltage Sensing Module","authors":"Hao Li, Hongmei Yu, Dongsheng Liu, Peng Liu, Bo Liu","doi":"10.1109/ASICON47005.2019.8983459","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983459","url":null,"abstract":"Spin transfer torque magnetic random access memory (STT-MRAM) is an emerging non-volatile memory and is regarded as a next generation memory. Efforts have been made in its write scheme, but the proposed schemes suffer from high write power and reliability issues. In this paper, we propose a low-power high-reliability write scheme with real-time voltage sensing and control module. Write operations are immediately terminated when the states of cells switch as desire, and when the current state match the state to be switched into, write operations will be terminated directly. The scheme is implemented and simulated in SMIC 40nm Logic Low Leakage process. Simulation results show that write power is 0.106pJ/bit on average, which is 62.5% less than the traditional scheme, and the effective judgment range of write “0” and write “1” is 408mV and 275mV respectively which is 3.15 times larger than the best previously result to our knowledge to reach high write reliability.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128599058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
ANN Based Adaptive Successive Cancellation List Decoder for Polar Codes 基于神经网络的极化码自适应逐次消去表解码器
2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/ASICON47005.2019.8983589
W. Song, Yuxiang Fu, Qinyu Chen, Li Li, Chuan Zhang
{"title":"ANN Based Adaptive Successive Cancellation List Decoder for Polar Codes","authors":"W. Song, Yuxiang Fu, Qinyu Chen, Li Li, Chuan Zhang","doi":"10.1109/ASICON47005.2019.8983589","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983589","url":null,"abstract":"Combined with cyclic redundancy check (CRC), SC list (SCL) decoder can achieve outstanding error correction performance, which is more obvious with increasing list size. However, the corresponding decoding complexity and latency increase with the list size. To this end, the selection of list size becomes essential for practical applications. A new artificial neural network (ANN) based framework is proposed in this paper to design a hardware-friendly adaptive SCL (DL-ASCL) decoder. First, the list size at each stage is predicted by an ANN predictor. The performance achieved based on the proposed DL-ASCL algorithm is close to the optimal SCL decoder with the same list size, especially in the high signal-to-noise ratio (SNR) region. Meanwhile, the computational complexity is significantly reduced compared with the conventional ones. Numerical results have demonstrated that the proposed deep learning based adaptive SCL decoder can achieve 56% computational complexity reduction compared with the conventional SCL decoder for the polar code with length 128 and rate 1/2. The hardware architecture of the adaptive SCL decoder based on the predicted list size is proposed and the folding technique is also adopted, which helps reduce the hardware cost by about 25%.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129272912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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