A FT Trimming Circuit Based on EPROM and Pin Multiplexing

Abstract

A Final Test (FT) trimming circuit with 4x8 bit single-layer polysilicon EPROM and Pin multiplexing is presented in this paper. The main part of the proposed circuit consists of Pin multiplexing circuit, power circuit of IP core, IIC logic and EPROM. The one-time programmable IP core is designed and implemented by IIC bus drive technology and FT trimming technology so as to achieve chip trimming and functional mode differentiation. The trimming circuit can effectively increase the programmability of the chip so as to reduce the influence of process offset and fluctuation, improving the yield and reliability of the chip. The proposed circuit has been successfully applied to a Li-ion battery protection integrated circuits (ICs) with a 0.18μ $m$ BCD process. The experimental results verify the reliability of the circuit and meet the performance requirements of circuit design.