BTI和工艺变化对组合电路冲击和监测的协同效应

2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI:10.1109/asicon47005.2019.8983690

Linzhe Li, Liyi Xiao, Jie Li, He Liu, Zhigang Mao

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引用次数: 1

摘要

随着技术节点的缩小，老化效应和工艺变化已成为集成电路可靠性的关键问题。本文分析了BTI效应和工艺变化对阈值电压的影响。然后由阈值电压的变化推导出逻辑门的延时和亚阈值电流的变化。最后，利用HSPICE在PTM 45nm模型上对逻辑门和ISCAS85电路进行了仿真。仿真结果显示了延迟和亚阈值电流随老化时间的变化关系，可用于预测电路参数的退化。通过测量亚阈值电流，可以快速监测电路延时的变化。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Synergistic Effect of BTI and Process Variations on Impact and Monitoring of Combination Circuit

With the technology node scaling down, aging effect and process variations have become the most critical reliability issues for integrated circuit. In this paper, the influence of BTI effect and process variation on threshold voltage is analyzed. Then, the delay of logic gate and the change of subthreshold current are deduced from the change of threshold voltage. Finally, the logic gate and ISCAS85 circuit are simulated by HSPICE in PTM 45nm model. Simulation results show the relationship between delay and subthreshold current with aging time, which can be used to predict the degradation of circuit parameters. The change of circuit delay can be quickly monitored by measuring subthreshold current.

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2019 IEEE 13th International Conference on ASIC (ASICON)

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