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2019 IEEE 13th International Conference on ASIC (ASICON)最新文献

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A Variation Aware Register Clustering Methodology in Near-Threshold Region 近阈值区域变化感知寄存器聚类方法
2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/ASICON47005.2019.8983494
Xiangnan Song, Shiying Zhang, Ju Zhou, Xuexiang Wang
{"title":"A Variation Aware Register Clustering Methodology in Near-Threshold Region","authors":"Xiangnan Song, Shiying Zhang, Ju Zhou, Xuexiang Wang","doi":"10.1109/ASICON47005.2019.8983494","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983494","url":null,"abstract":"Near threshold voltage (NTV) design has gained significant attention due to its optimal energy efficiency. However, circuits are highly sensitive to process variations at NTV, which poses great challenges for clock network design. In this paper, we propose a variation aware register clustering methodology for clock network design at NTV. The timing-driven and load-balanced methods are implemented to reduce clock skew and sensitivity to process variation of clock skew at NTV. Experiment results show that our algorithms reduce the skew by 37.7% and skew variation (σ) by 16.4% with only 3.2% increase on power consumption.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124325179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High precision low power CMOS bandgap for RFID 用于RFID的高精度低功耗CMOS带隙
2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/ASICON47005.2019.8983448
Xian Zhang, Yong Xu
{"title":"High precision low power CMOS bandgap for RFID","authors":"Xian Zhang, Yong Xu","doi":"10.1109/ASICON47005.2019.8983448","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983448","url":null,"abstract":"In this paper, a low power high precision bandgap reference with a third-order temperature compensation and a high slope positive-temperature coefficient voltage are designed using a SMIC 180 nm BiCMOS process. The structure of positive temperature coefficient current and negative temperature coefficient current subtraction are used to obtain a high slope positive temperature coefficient current, which is more convenient for sampling of the rear circuit. The simulation show when the temperature is changed within the range of −25 to 100 °C, the temperature coefficient of the output reference voltage is 3.8ppm/°C, the slope of the PTAT voltage is 5.13mV/°C the PSRR at low frequency is −62dB. At a power supply voltage of 1.8V, the overall power consumption is 50uW.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126268778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Optimal Designed Compensator for PSR Flyback Converters Based on Genetic Algorithm 基于遗传算法的PSR反激变换器补偿器优化设计
2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/ASICON47005.2019.8983651
Tianyuan Tang, Ping Luo, Chengda Deng, Qiang Wang, Liao Zhang, Bo Zhang
{"title":"An Optimal Designed Compensator for PSR Flyback Converters Based on Genetic Algorithm","authors":"Tianyuan Tang, Ping Luo, Chengda Deng, Qiang Wang, Liao Zhang, Bo Zhang","doi":"10.1109/ASICON47005.2019.8983651","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983651","url":null,"abstract":"Primary side regulated flyback eliminates opto-coupler and can realize multipath output. The parameters of compensator for stable flyback are quite difficult for manual calculation, especially when other parameters of circuit vary a lot. This paper proposes an optimal designed compensator based on genetic algorithm. A detailed process of calculation from model building to algorithm operators using has been explained. The results gotten from genetic algorithm has been approved by simulation in Matlab and Cadence. The CV PSR flyback has a good dynamic performance and small ripple of output voltage under different loads.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126301692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Non-linear function evaluation reusing matrix-vector multipliers 非线性函数评估重用矩阵-向量乘法器
2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/ASICON47005.2019.8983557
Ce Guo, W. Luk, Wenguang Xu
{"title":"Non-linear function evaluation reusing matrix-vector multipliers","authors":"Ce Guo, W. Luk, Wenguang Xu","doi":"10.1109/ASICON47005.2019.8983557","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983557","url":null,"abstract":"This paper presents a method to extend matrix-vector multipliers to support the evaluation of non-linear functions. The proposed approach introduces non-linearity by optionally overriding the input signals of the matrix-vector multiplier. The method aims to reduce the idleness of hardware resources during computation, to maximise the reuse of arithmetic units and internal structures in existing matrix-vector multipliers, and to reduce the effort in adding additional functions. From our analysis on a case with eight non-linear functions, the proposed design consumes fewer components for addition, multiplication, division, exponentiation and logarithm than a reference design with dedicated function evaluation facilities.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128132201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Variation Analysis of Interconnect Capacitance and Process Corner in Advanced CMOS Process with Double Patterning Technology 双图先进CMOS工艺中互连电容和工艺角的变化分析
2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/asicon47005.2019.8983474
Zhimei Cai, Zhiyong Han, Ming Tian, Changfeng Wang, X. Hu, R. Cheng, Yi Zhao
{"title":"Variation Analysis of Interconnect Capacitance and Process Corner in Advanced CMOS Process with Double Patterning Technology","authors":"Zhimei Cai, Zhiyong Han, Ming Tian, Changfeng Wang, X. Hu, R. Cheng, Yi Zhao","doi":"10.1109/asicon47005.2019.8983474","DOIUrl":"https://doi.org/10.1109/asicon47005.2019.8983474","url":null,"abstract":"Double patterning lithography is an important solution for critical layers with sub-64nm pitch interconnects. The overlay created by double patterning technology could add an extra capacitance variation, which increases the complexity of parasitic capacitance extractions. In this study, we mainly analyzed the effect of double patterning overlay on the intra-layer capacitance, inter-layer capacitance and process corner.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132561889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Temperature Dependence of Bias Temperature Instability (BTI) in Long-term Measurement by BTI-sensitive and -insensitive Ring Oscillators Removing Environmental Fluctuation 消除环境波动的偏置温度不稳定性(BTI)敏感和不敏感环振长期测量中的温度依赖性
2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/ASICON47005.2019.8983438
Takuya Asuke, Ryo Kishida, J. Furuta, Kazutoshi Kobayashi
{"title":"Temperature Dependence of Bias Temperature Instability (BTI) in Long-term Measurement by BTI-sensitive and -insensitive Ring Oscillators Removing Environmental Fluctuation","authors":"Takuya Asuke, Ryo Kishida, J. Furuta, Kazutoshi Kobayashi","doi":"10.1109/ASICON47005.2019.8983438","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983438","url":null,"abstract":"Measuring bias temperature instability (BTI) on ring oscillators (ROs) is frequently used. However, performance of a semiconductor chip is fluctuated dynamically due to bias, temperature and etc. BTI-sensitive and -insensitive ROs are implemented in order to extract BTI-induced degradation without those temporal fluctuation factors. A test chip including those ROs was fabricated in a 65 nm process and residual components without fluctuation could be extracted. The well-known power-law model of BTI with time exponent $n = 1/6$ is extracted from smooth degradation curves.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134214106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Flash-based Computing in-Memory Scheme for IOT 基于闪存的物联网内存计算方案
2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/ASICON47005.2019.8983502
J. Kang, Peng Huang, Runze Han, Y. Xiang, X. L. Cui, X. Liu
{"title":"Flash-based Computing in-Memory Scheme for IOT","authors":"J. Kang, Peng Huang, Runze Han, Y. Xiang, X. L. Cui, X. Liu","doi":"10.1109/ASICON47005.2019.8983502","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983502","url":null,"abstract":"A novel flash-based computing in-memory scheme is presented to accelerate the multiply-accumulate (MAC) operation. Based on the novel scheme the hardware implementation and optimization object-oriented deep leaning neuron networks (DNN) is explored to achieve computation power with high efficiency and low power. Based on a 65nm node flash process, a 5-layer DNN is designed and evaluated by simulation to verify the feasibility of the presented flash-based computing in-memory scheme and the corresponding hardware implementations for the low power edge computing applications such as internet of things (IoT).","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133894657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A Polymorphic Circuit Interoperability Framework 多态电路互操作性框架
2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/ASICON47005.2019.8983594
Timothy Dunlap, G. Qu, Jinmei Lai
{"title":"A Polymorphic Circuit Interoperability Framework","authors":"Timothy Dunlap, G. Qu, Jinmei Lai","doi":"10.1109/ASICON47005.2019.8983594","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983594","url":null,"abstract":"The Polymorphic Circuit Interoperability Framework is presented in this paper. This framework separates the polymorphic component (called the polymorphic element) from the functional gates (called the switchable gate). The requirement of the framework is that the polymorphic element outputs a non-empty set of signals that change based on the polymorphic effect desired. In this paper, single output polymorphic elements based on voltage and clock speed are shown, and a polymorphic element based on temperature is theoretically adapted from existing literature [5]. A switchable gate that implements NAND/NOR functionality is shown and used with these polymorphic elements to test the framework for polymorphic functionality. The results are presented and polymorphic functionality is successfully demonstrated.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134375198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Efficient ASIC Implementation of Public Key Cryptography Algorithm SM2 Based on Module Arithmetic Logic Unit 基于模块算术逻辑单元的公钥加密算法SM2的高效ASIC实现
2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/ASICON47005.2019.8983471
Danyang Yang, Z. Dai, Wei Li, Tao Chen
{"title":"An Efficient ASIC Implementation of Public Key Cryptography Algorithm SM2 Based on Module Arithmetic Logic Unit","authors":"Danyang Yang, Z. Dai, Wei Li, Tao Chen","doi":"10.1109/ASICON47005.2019.8983471","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983471","url":null,"abstract":"SM2 public key cryptography, proposed by China, is widely used to ensure the security in communication. In this paper, based on the module arithmetic logic unit, SM3 unit, verify unit and XOR unit, we implemented a dual-field processor over SM2 public key cryptography, which can complete digital signature, verification, information encryption and decryption. In addition, the SM2 processor is described by Verilog HDL, and synthesized in CMOS 55nm process. Experimental results show that the SM2 processor runs at high frequency of 476 MHz with area of 245K gates. What's more, the processor requires only 0.56ms to compute a 256-bit point multiplication in GF(p), and 0.59ms in GF(2m).","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126597048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Web-based Waveform Viewer for BR0101 Chip Testing Platform 基于web的BR0101芯片测试平台波形查看器
2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/ASICON47005.2019.8983579
Xinyu He, Xie Xie, Jinmei Lai, Jian Wang
{"title":"A Web-based Waveform Viewer for BR0101 Chip Testing Platform","authors":"Xinyu He, Xie Xie, Jinmei Lai, Jian Wang","doi":"10.1109/ASICON47005.2019.8983579","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983579","url":null,"abstract":"Visualization software can convert circuit testing results into waveform images. In this paper a web-based waveform visualization software package is proposed by using Python as backend data parser and JavaScript to create lines in frontend HTML canvas images. Control of waveform is introduced with JavaScript functions. This visualization package has no dependencies on local software other than browsers, and can complete waveform depiction in 68.2ms on average by applying lazy evaluation in frontend drawing process.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130875549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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