双图先进CMOS工艺中互连电容和工艺角的变化分析

2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI:10.1109/asicon47005.2019.8983474

Zhimei Cai, Zhiyong Han, Ming Tian, Changfeng Wang, X. Hu, R. Cheng, Yi Zhao

{"title":"双图先进CMOS工艺中互连电容和工艺角的变化分析","authors":"Zhimei Cai, Zhiyong Han, Ming Tian, Changfeng Wang, X. Hu, R. Cheng, Yi Zhao","doi":"10.1109/asicon47005.2019.8983474","DOIUrl":null,"url":null,"abstract":"Double patterning lithography is an important solution for critical layers with sub-64nm pitch interconnects. The overlay created by double patterning technology could add an extra capacitance variation, which increases the complexity of parasitic capacitance extractions. In this study, we mainly analyzed the effect of double patterning overlay on the intra-layer capacitance, inter-layer capacitance and process corner.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Variation Analysis of Interconnect Capacitance and Process Corner in Advanced CMOS Process with Double Patterning Technology\",\"authors\":\"Zhimei Cai, Zhiyong Han, Ming Tian, Changfeng Wang, X. Hu, R. Cheng, Yi Zhao\",\"doi\":\"10.1109/asicon47005.2019.8983474\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Double patterning lithography is an important solution for critical layers with sub-64nm pitch interconnects. The overlay created by double patterning technology could add an extra capacitance variation, which increases the complexity of parasitic capacitance extractions. In this study, we mainly analyzed the effect of double patterning overlay on the intra-layer capacitance, inter-layer capacitance and process corner.\",\"PeriodicalId\":319342,\"journal\":{\"name\":\"2019 IEEE 13th International Conference on ASIC (ASICON)\",\"volume\":\"58 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE 13th International Conference on ASIC (ASICON)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/asicon47005.2019.8983474\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE 13th International Conference on ASIC (ASICON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/asicon47005.2019.8983474","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

双图纹光刻技术对于具有低于64nm间距互连的关键层是重要的解决方案。双图案技术产生的覆盖层会增加额外的电容变化，这增加了寄生电容提取的复杂性。在本研究中，我们主要分析了双图纹叠加对层内电容、层间电容和工艺角的影响。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Variation Analysis of Interconnect Capacitance and Process Corner in Advanced CMOS Process with Double Patterning Technology

Double patterning lithography is an important solution for critical layers with sub-64nm pitch interconnects. The overlay created by double patterning technology could add an extra capacitance variation, which increases the complexity of parasitic capacitance extractions. In this study, we mainly analyzed the effect of double patterning overlay on the intra-layer capacitance, inter-layer capacitance and process corner.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2019 IEEE 13th International Conference on ASIC (ASICON)

自引率

0.00%

发文量