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Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)最新文献

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Integrated mixer design 一体化混频器设计
Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) Pub Date : 2000-08-28 DOI: 10.1109/APASIC.2000.896936
Glenn Watanabe, H. Lau, Juergen Schoepf
{"title":"Integrated mixer design","authors":"Glenn Watanabe, H. Lau, Juergen Schoepf","doi":"10.1109/APASIC.2000.896936","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896936","url":null,"abstract":"Several RF mixer topologies that can be realized in CMOS and BiCMOS integrated circuits are presented. Their performance with regard to gain, noise figure, linearity, dynamic range and port-to-port isolation are reviewed and compared. A proposed figure of merit on the designs is presented for system design and performance tradeoff considerations.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127336675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Design of an equalizer using the DFE structure and the MMA algorithm 利用DFE结构和MMA算法设计均衡器
Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) Pub Date : 2000-08-28 DOI: 10.1109/APASIC.2000.896942
D. Shin, Seung Joong Hwang, Byoung-Gak Jo, M. Sunwoo
{"title":"Design of an equalizer using the DFE structure and the MMA algorithm","authors":"D. Shin, Seung Joong Hwang, Byoung-Gak Jo, M. Sunwoo","doi":"10.1109/APASIC.2000.896942","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896942","url":null,"abstract":"This paper proposes an equalizer using MMA (MultiModulus Algorithm) and LMS (Least Mean Square) algorithms and uses a DFE (Decision Feedback Equalizer) structure. The existing MMA equalizer uses two transversal filters but the proposed equalizer uses two DFE filter banks to improve the channel adaptive performance and to reduce the number of taps. The fabricated equalizer ASIC chip using the MMA and LMS algorithms operates at 8 MHz and provides 64 Mbps which is higher than existing equalizers. The chip uses the 0.35 /spl mu/m technology and has about 160000 gates.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121944195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A hardware reduced multiplier for low power design 一种用于低功耗设计的硬件简化乘法器
Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) Pub Date : 2000-08-28 DOI: 10.1109/APASIC.2000.896975
Kwang-Hyun Lee, C. Rim
{"title":"A hardware reduced multiplier for low power design","authors":"Kwang-Hyun Lee, C. Rim","doi":"10.1109/APASIC.2000.896975","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896975","url":null,"abstract":"In this paper, we proposed a hardware reduced multiplier for DSP applications. In many DSP applications, all multiplier output bits were not used, but only upper bits of output were used. Kidambi [1995] proposed a truncated unsigned multiplier for this idea. In this paper, we adopt this truncation scheme for a Booth multiplier which can be used in real DSP systems more efficiently. Also, our truncated Booth multiplier guaranteed 0 input to 0 output that was not provided in previous papers. Truncated Booth multiplier reduced area by about 37.48% and power consumption by about 44%.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131052217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Interconnect strategy in deep-submicron DRAM technology 深亚微米DRAM技术中的互连策略
Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) Pub Date : 2000-08-28 DOI: 10.1109/APASIC.2000.896979
J. Wee, Si-Hong Kim, YongKeun Park, Sejun Kim, Jin-Yong Chung
{"title":"Interconnect strategy in deep-submicron DRAM technology","authors":"J. Wee, Si-Hong Kim, YongKeun Park, Sejun Kim, Jin-Yong Chung","doi":"10.1109/APASIC.2000.896979","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896979","url":null,"abstract":"This paper discusses the interconnect-related issues and general approaches in deep submicron technology. First, issues on interconnect library generation including simulations and measurements are discussed. Second, issues related to library-generating tools, which include parasitics extracting tools for early design stage and post-design stage, are analyzed. Third, issues are focused on design automation including chip floorplanner, interconnect-buffer optimizer, interconnect routing optimizer and so on. Finally we discuss our approach in DRAM technology. These interconnect-related items are relevant to chip families such as memory and logic device owing to hierarchical design concept, performance, cost, design-turn around times and so on.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117323596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Adaptive AC/DC output buffer with reduced ground bounce and output ringing 自适应交流/直流输出缓冲器，减少地面反弹和输出振铃
Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) Pub Date : 2000-08-28 DOI: 10.1109/APASIC.2000.896909
S. Jou, Shu-Hua Kuo, J. Chiu, V. Lin
{"title":"Adaptive AC/DC output buffer with reduced ground bounce and output ringing","authors":"S. Jou, Shu-Hua Kuo, J. Chiu, V. Lin","doi":"10.1109/APASIC.2000.896909","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896909","url":null,"abstract":"A CMOS output buffer with AC and DC stages and adaptively feedback control scheme is proposed. Implementation results show that it can reduce the output ring by 60%, power/GND line bounce by 40% for the case of 2 ns rise and fall time with 40 pF output loading.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"28 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132833262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A novel architecture of rake receiver for fast acquisition 一种新的快速采集rake接收机结构
Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) Pub Date : 2000-08-28 DOI: 10.1109/APASIC.2000.896956
Jungmin Ro, Seongjoo Lee, Jaeseok Kim, I. Eo, Kyungsoo Kim
{"title":"A novel architecture of rake receiver for fast acquisition","authors":"Jungmin Ro, Seongjoo Lee, Jaeseok Kim, I. Eo, Kyungsoo Kim","doi":"10.1109/APASIC.2000.896956","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896956","url":null,"abstract":"We investigate the rake receiver design alternatives for CDMA systems. The main objective of this paper is to find ways to achieve the rake receiver for both fast PN code acquisition and minimizing hardware complexity and power consumption. We design a searching finger to enhance the speed of the initial PN code acquisition. The searching finger is used as a searcher in the initial acquisition and as a finger after the initial acquisition. The results indicate that, without introducing significant hardware increments, the acquisition is faster twice than that of the conventional rake receiver.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134271740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A dual-band receiver architecture for PCS and IMT-2000 用于pc和IMT-2000的双频接收器架构
Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) Pub Date : 2000-08-28 DOI: 10.1109/APASIC.2000.896952
Sang-Gug Lee, Namsoo Kim, Seung-Min Oh, Jeongki Choi, Sin-Churl Kim
{"title":"A dual-band receiver architecture for PCS and IMT-2000","authors":"Sang-Gug Lee, Namsoo Kim, Seung-Min Oh, Jeongki Choi, Sin-Churl Kim","doi":"10.1109/APASIC.2000.896952","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896952","url":null,"abstract":"A dual-band receiver architecture for PCS and IMT-2000 is described. The proposed architecture is suitable for high-level integration and minimizes the hardware duplicity by adopting a single wide-band high-performance image-rejection mixer in conjunction with a frequency doubler. Along with the architectural aspects of the dual-band receiver, the circuit implementation details are described.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129653349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
VLSI implementation of an OFB processor for encryption of real-time data 一种用于实时数据加密的OFB处理器的VLSI实现
Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) Pub Date : 2000-08-28 DOI: 10.1109/APASIC.2000.896938
Young-Chul Kim, Kwang-Ok Kim, Tae-Won Lee
{"title":"VLSI implementation of an OFB processor for encryption of real-time data","authors":"Young-Chul Kim, Kwang-Ok Kim, Tae-Won Lee","doi":"10.1109/APASIC.2000.896938","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896938","url":null,"abstract":"In this paper, the OFB processor, which encrypts real-time data (stream type) on a noisy channel such as satellite communication, is implemented. We design four main blocks, which are Key Interface block, DES block of two-round method, Shift Reg block and Sel discard block necessary for implementation of the OFB processor. These blocks are modeled in VHDL and verified by simulation and synthesis. The proposed OFB processor is designed in full-custom by 0.6 mm Hyun Dai fabrication using the IDEC-C631 library.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"04 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129672101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
CSPL: a capacitor-separated pass-transistor logic 电容分离通管逻辑
Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) Pub Date : 2000-08-28 DOI: 10.1109/APASIC.2000.896900
T. Yamashita, K. Asada
{"title":"CSPL: a capacitor-separated pass-transistor logic","authors":"T. Yamashita, K. Asada","doi":"10.1109/APASIC.2000.896900","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896900","url":null,"abstract":"In this study, a method for reducing delay time in a pass-transistor circuit is proposed, where capacitor and latching sense amplifier for pass-transistor logic are used. The coupling capacitor realizes the setting of the optimum bias and supply voltage in each pass-transistor and sense amp. We show the circuit operated 9.5 times as fast as the conventional CMOS circuits for typical applications at 1.2 V.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130007728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
VLSI processor of parallel genetic algorithm VLSI处理器的并行遗传算法
Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) Pub Date : 2000-08-28 DOI: 10.1109/APASIC.2000.896929
Y. Choi, Duck-Jin Chung
{"title":"VLSI processor of parallel genetic algorithm","authors":"Y. Choi, Duck-Jin Chung","doi":"10.1109/APASIC.2000.896929","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896929","url":null,"abstract":"In this paper, we proposed a hardware-oriented parallel genetic algorithm processor (GAP). It is a more efficient parallel GAP based on the steady-state GA with modified tournament selection. In addition, our design was applied to the parallelisms of coarse-grain and fine-grain for parallel and distributed processing in the pursuit of even better performance than the single GAP. In this paper, the proposed parallel GAP is implemented on the PCIGEN10K board with two EFP10K100A240-1 devices. The proposed parallel GAP (2-processor) increased the speed of finding the optimal solution by about 50% more than the single GAP.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132543079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
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