Interconnect strategy in deep-submicron DRAM technology

This paper discusses the interconnect-related issues and general approaches in deep submicron technology. First, issues on interconnect library generation including simulations and measurements are discussed. Second, issues related to library-generating tools, which include parasitics extracting tools for early design stage and post-design stage, are analyzed. Third, issues are focused on design automation including chip floorplanner, interconnect-buffer optimizer, interconnect routing optimizer and so on. Finally we discuss our approach in DRAM technology. These interconnect-related items are relevant to chip families such as memory and logic device owing to hierarchical design concept, performance, cost, design-turn around times and so on.