利用DFE结构和MMA算法设计均衡器

Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) Pub Date : 2000-08-28 DOI:10.1109/APASIC.2000.896942

D. Shin, Seung Joong Hwang, Byoung-Gak Jo, M. Sunwoo

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引用次数: 0

摘要

本文提出了一种基于MMA(多模算法)和LMS(最小均方)算法的均衡器，并采用了DFE(决策反馈均衡器)结构。现有的MMA均衡器使用两个横向滤波器，而提出的均衡器使用两个DFE滤波器组来提高信道自适应性能并减少抽头数量。采用MMA和LMS算法制作的均衡器ASIC芯片工作频率为8 MHz，提供比现有均衡器更高的64 Mbps。该芯片采用0.35 /spl mu/m技术，拥有约16万个栅极。

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Design of an equalizer using the DFE structure and the MMA algorithm

This paper proposes an equalizer using MMA (MultiModulus Algorithm) and LMS (Least Mean Square) algorithms and uses a DFE (Decision Feedback Equalizer) structure. The existing MMA equalizer uses two transversal filters but the proposed equalizer uses two DFE filter banks to improve the channel adaptive performance and to reduce the number of taps. The fabricated equalizer ASIC chip using the MMA and LMS algorithms operates at 8 MHz and provides 64 Mbps which is higher than existing equalizers. The chip uses the 0.35 /spl mu/m technology and has about 160000 gates.

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Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)

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