Sang-Gug Lee, Namsoo Kim, Seung-Min Oh, Jeongki Choi, Sin-Churl Kim
{"title":"用于pc和IMT-2000的双频接收器架构","authors":"Sang-Gug Lee, Namsoo Kim, Seung-Min Oh, Jeongki Choi, Sin-Churl Kim","doi":"10.1109/APASIC.2000.896952","DOIUrl":null,"url":null,"abstract":"A dual-band receiver architecture for PCS and IMT-2000 is described. The proposed architecture is suitable for high-level integration and minimizes the hardware duplicity by adopting a single wide-band high-performance image-rejection mixer in conjunction with a frequency doubler. Along with the architectural aspects of the dual-band receiver, the circuit implementation details are described.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A dual-band receiver architecture for PCS and IMT-2000\",\"authors\":\"Sang-Gug Lee, Namsoo Kim, Seung-Min Oh, Jeongki Choi, Sin-Churl Kim\",\"doi\":\"10.1109/APASIC.2000.896952\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A dual-band receiver architecture for PCS and IMT-2000 is described. The proposed architecture is suitable for high-level integration and minimizes the hardware duplicity by adopting a single wide-band high-performance image-rejection mixer in conjunction with a frequency doubler. Along with the architectural aspects of the dual-band receiver, the circuit implementation details are described.\",\"PeriodicalId\":313978,\"journal\":{\"name\":\"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-08-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APASIC.2000.896952\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APASIC.2000.896952","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A dual-band receiver architecture for PCS and IMT-2000
A dual-band receiver architecture for PCS and IMT-2000 is described. The proposed architecture is suitable for high-level integration and minimizes the hardware duplicity by adopting a single wide-band high-performance image-rejection mixer in conjunction with a frequency doubler. Along with the architectural aspects of the dual-band receiver, the circuit implementation details are described.