电容分离通管逻辑

Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) Pub Date : 2000-08-28 DOI:10.1109/APASIC.2000.896900

T. Yamashita, K. Asada

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引用次数: 1

摘要

在本研究中，提出一种减少通管电路延迟时间的方法，该方法使用通管逻辑的电容和锁存感测放大器。耦合电容实现了每个通管和感测放大器的最佳偏置和供电电压的设置。我们展示了该电路在1.2 V的典型应用中比传统CMOS电路工作速度快9.5倍。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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CSPL: a capacitor-separated pass-transistor logic

In this study, a method for reducing delay time in a pass-transistor circuit is proposed, where capacitor and latching sense amplifier for pass-transistor logic are used. The coupling capacitor realizes the setting of the optimum bias and supply voltage in each pass-transistor and sense amp. We show the circuit operated 9.5 times as fast as the conventional CMOS circuits for typical applications at 1.2 V.

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Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)

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