CSPL: a capacitor-separated pass-transistor logic

Abstract

In this study, a method for reducing delay time in a pass-transistor circuit is proposed, where capacitor and latching sense amplifier for pass-transistor logic are used. The coupling capacitor realizes the setting of the optimum bias and supply voltage in each pass-transistor and sense amp. We show the circuit operated 9.5 times as fast as the conventional CMOS circuits for typical applications at 1.2 V.