72nd Device Research Conference最新文献

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Plasmonic and metallic cavity nanolasers: A new paradigm for semiconductor lasers? 等离子体和金属腔纳米激光器:半导体激光器的新范式?
72nd Device Research Conference Pub Date : 2014-06-22 DOI: 10.1109/DRC.2014.6872286
C. Ning, K. Ding
{"title":"Plasmonic and metallic cavity nanolasers: A new paradigm for semiconductor lasers?","authors":"C. Ning, K. Ding","doi":"10.1109/DRC.2014.6872286","DOIUrl":"https://doi.org/10.1109/DRC.2014.6872286","url":null,"abstract":"In this paper, a summary overview of mostly authors' efforts since 2006 in developing the metallic cavity nanolasers is presented. It will start with a brief overview of short history and a background introduction to the plasmon-photon interactions, showing how such interactions might lead to a nanolaser of ever shrinking size. Recent progress in theoretical and experimental studies will then be presented, including the demonstration of the first nanolaser with size below the diffraction limit our recent efforts in raising the operating temperature of such nanolasers, and the eventual realization of the first continuous-wave operation of subwavelength size nanolasers at room temperature under electrical injection.","PeriodicalId":293780,"journal":{"name":"72nd Device Research Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114183244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Experimental demonstration of inverter and NAND operation in p-TFET logic at ultra-low supply voltages down to VDD = 0.15 V 超低电源电压VDD = 0.15 V下p-TFET逻辑下逆变器和NAND工作的实验演示
72nd Device Research Conference Pub Date : 2014-06-22 DOI: 10.1109/DRC.2014.6872281
S. Richter, C. Schulte-Braucks, L. Knoll, G. V. Luong, A. Schafer, S. Trellenkamp, Qing-Tai Zhao, S. Mantl
{"title":"Experimental demonstration of inverter and NAND operation in p-TFET logic at ultra-low supply voltages down to VDD = 0.15 V","authors":"S. Richter, C. Schulte-Braucks, L. Knoll, G. V. Luong, A. Schafer, S. Trellenkamp, Qing-Tai Zhao, S. Mantl","doi":"10.1109/DRC.2014.6872281","DOIUrl":"https://doi.org/10.1109/DRC.2014.6872281","url":null,"abstract":"Tunnel-FETs (TFETs) have been studied extensively as a replacement for MOSFETs in the supply voltage regime below VDD = 0.3 V [1]. Due to the TFET ability for offering inverse subthreshold slopes SS below 60 mV/dec, these devices are promising candidates for power efficient integrated circuits. Extensive research has been carried out on the characteristics of single TFET devices [2][3] and first inverter structures have been realized as demonstration of simple logic circuits [4][5][6]. In this work, we present TFET logic circuits based on gate-all-around (GAA) Si nanowire (NW) array TFETs showing small SS and high Ion of 39 μA/μm at VDD = -1 V. This comparably high performance in Si TFETs was realized by a source formation via silicidation and dopant segregation. Using these devices inverters based on p-TFET logic and for the first time TFET NAND gates are demonstrated experimentally. The logic gates operate at ultra-low supply voltages down to VDD = 0.15 V.","PeriodicalId":293780,"journal":{"name":"72nd Device Research Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115949858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Modulation of over 1014 cm−2 electrons at the SrTiO3/GdTiO3 heterojunction SrTiO3/GdTiO3异质结中超过1014 cm−2电子的调制
72nd Device Research Conference Pub Date : 2014-06-22 DOI: 10.1109/DRC.2014.6872276
O. Shoron, M. Boucherit, C. Jackson, T. Cain, M. Buffon, C. Polchinski, S. Stemmer, S. Rajan
{"title":"Modulation of over 1014 cm−2 electrons at the SrTiO3/GdTiO3 heterojunction","authors":"O. Shoron, M. Boucherit, C. Jackson, T. Cain, M. Buffon, C. Polchinski, S. Stemmer, S. Rajan","doi":"10.1109/DRC.2014.6872276","DOIUrl":"https://doi.org/10.1109/DRC.2014.6872276","url":null,"abstract":"The polar discontinuity <sup>[1]</sup> and electronic reconstruction at the interface of SrTiO3 and GdTiO3 leads to a unique high two dimensional electron gas (2DEG) of 3×10<sup>14</sup> electron/cm<sup>2[2]</sup>, that is exactly half of the number of unit cells at the interface. The ability to modulate this high charge density could enable a new class of oxide electronics and plasmonics devices that harness extreme charge density. In this work show how heterostructures field effect transistors can be designed to enable modulation of over 10<sup>14</sup> cm<sup>-2</sup> electron/cm<sup>2</sup>, where represents the highest charge density modulated in any field effector transistor to date.","PeriodicalId":293780,"journal":{"name":"72nd Device Research Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131120910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Surface transport and DC current gain in InGaAs/InP DHBTs for THz applications 太赫兹应用中InGaAs/InP dhbt的表面输运和直流电流增益
72nd Device Research Conference Pub Date : 2014-06-22 DOI: 10.1109/DRC.2014.6872345
H. Chiang, J. Rode, P. Choudhary, M. Rodwell
{"title":"Surface transport and DC current gain in InGaAs/InP DHBTs for THz applications","authors":"H. Chiang, J. Rode, P. Choudhary, M. Rodwell","doi":"10.1109/DRC.2014.6872345","DOIUrl":"https://doi.org/10.1109/DRC.2014.6872345","url":null,"abstract":"InGaAs/InP double heterojunction bipolar transistors (DHBTs) are highly suitable for applications in GHz mixed-signal ICs, >100 GHz digital logic, and millimeter-wave communications and imaging because of their high breakdown voltage and high cutoff frequencies (fτ/fmax~0.5/1.0 THz)[1,2]. To extend HBT bandwidth, device dimensions must be reduced and the doping concentration in the InGaAs base must be increased. As a result, surface recombination increases, as does lateral electron transport from the emitter to the base contact, both on the exposed base surface and within the bulk base semiconductor. The DC current gain (β) thus decreases. Experimentally measured β are ~10-25 in THz DHBTs [2]. Because it limits the useful range of circuit applications, it is important to understand the mechanisms causing decreased β in scaled DHBTs. Using TCAD simulation, we had earlier found that lateral carrier diffusion within the bulk of the base contributes significantly to the observed high base currents in THz HBTs [3]. Here we model the surface conduction between the emitter and base contacts resulting from Fermi level pinning at the exposed base semiconductor surface, comparing simulations with experimental data. At bias conditions corresponding to peak fτ/fmax, we find that ~50% of the total base current arises from surface conduction. This finding suggests the need for improved base surface passivation in THz HBTs.","PeriodicalId":293780,"journal":{"name":"72nd Device Research Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127547559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Performance analysis of different SRAM cell topologies employing tunnel-FETs 采用隧道场效应管的不同SRAM单元拓扑的性能分析
72nd Device Research Conference Pub Date : 2014-06-22 DOI: 10.1109/DRC.2014.6872338
S. Strangio, P. Palestri, D. Esseni, L. Selmi, F. Crupi
{"title":"Performance analysis of different SRAM cell topologies employing tunnel-FETs","authors":"S. Strangio, P. Palestri, D. Esseni, L. Selmi, F. Crupi","doi":"10.1109/DRC.2014.6872338","DOIUrl":"https://doi.org/10.1109/DRC.2014.6872338","url":null,"abstract":"Tunnel-FET is one of the most promising candidates to replace CMOS in low-power (LP) applications [1], featuring a sub-threshold slope (SS) below the 60mV/dec limit of MOSFET. However, the intrinsic asymmetry of TFETs, makes them good transistors only for a current flowing from drain to source and prevents their use as access transistors (AT) in the 6T SRAM cell. In this paper, we use TCAD mixed device-circuit simulations [2] of symmetric 6T SRAM cells, implemented with the n-type SiGe/Si TFET and p-type strained-Si TFET designed in [3] (Fig. 1) for VDD as low as 0.2V. The gate metal work-functions were set to match the off-current for LP applications (10pA/μm). For comparison purposes, both N- and P-MOS were also designed with the same double-gate SOI structure. The ID-VGS curves of the TFETs (Fig.2) show that the sub-60mV/decade region is confined to ultra low voltage regime (below 0.25 V) and that ambipolarity is very limited in these devices. ID(VDS) in Fig.3 show the lower output conductance of the TFETs w.r.t. to MOS.","PeriodicalId":293780,"journal":{"name":"72nd Device Research Conference","volume":"1 24","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114044509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Monolithically patterned high mobility solution-processed metal-oxide TFTs with metallic capping layers 具有金属盖层的单片高迁移率溶液加工金属氧化物tft
72nd Device Research Conference Pub Date : 2014-06-22 DOI: 10.1109/DRC.2014.6872335
Kyung‐Tae Kim, Jae Hyun Kim, I. Jang, Chanho Jo, Jaekyun Kim, Yong‐Hoon Kim, S. Park
{"title":"Monolithically patterned high mobility solution-processed metal-oxide TFTs with metallic capping layers","authors":"Kyung‐Tae Kim, Jae Hyun Kim, I. Jang, Chanho Jo, Jaekyun Kim, Yong‐Hoon Kim, S. Park","doi":"10.1109/DRC.2014.6872335","DOIUrl":"https://doi.org/10.1109/DRC.2014.6872335","url":null,"abstract":"Amorphous indium gallium zinc oxide(IGZO) based thin film transistors(TFTs) have been widely studied due to their good electrical properties such as optical transparent and field effect mobility. The demand for low-cost process of thin film devices has needed solution processed metal oxide TFTs. Although many effective ways of fabricating soluble metal oxide TFTs have been investigated1, there is still the necessity of increasing field effect mobility of TFTs. As a one way of mobility improvement, low work function metals(Ca, Ti) were used as passivation in terms of capping layer on top of the IGZO active layer2,3. The metal capping method has obvious several advantages, but we expect the additional process cost due to a step of patterning the capping layer. Also, because nature of metals has no transparent characteristics, this pure metal capping method could not available in transparent applications. In this paper, we suggest a real time deposition method of electrodes and capping layer for solution processed IGZO TFTs with maintaining transparency and process cost.","PeriodicalId":293780,"journal":{"name":"72nd Device Research Conference","volume":"317 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124292580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Observation of impact ionization at sub-0.5V and resultant improvement in ideality in I-NPN selector device by Si epitaxy for RRAM applications RRAM用Si外延对I-NPN选择器中低于0.5 v冲击电离的观察及其理想性的改善
72nd Device Research Conference Pub Date : 2014-06-22 DOI: 10.1109/DRC.2014.6872336
B. Das, R. Meshram, V. Ostwal, J. Schulze, U. Ganguly
{"title":"Observation of impact ionization at sub-0.5V and resultant improvement in ideality in I-NPN selector device by Si epitaxy for RRAM applications","authors":"B. Das, R. Meshram, V. Ostwal, J. Schulze, U. Ganguly","doi":"10.1109/DRC.2014.6872336","DOIUrl":"https://doi.org/10.1109/DRC.2014.6872336","url":null,"abstract":"The improvement in ideality is demonstrated by impact ionization at sub-0.5V in silicon despite the higher 1eV band-gap. The NIPIN structure produces high internal field due to the built-in potential (~1eV) of the junctions in addition to Va (cf. a simple pn junction in IMOS) which provides electron sufficient (>bandgap) energy for II. In addition, the dopant profile engineering with i-region to increase scattering length is possibly responsible to effective Impact Ionization at low bias enabling record low bias II (Table 1 that is attractive for advanced memory and logic.","PeriodicalId":293780,"journal":{"name":"72nd Device Research Conference","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116645399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Memristive synaptic plasticity in Pr0.7Ca0.3MnO3 RRAM by bio-mimetic programming 基于仿生编程的Pr0.7Ca0.3MnO3 RRAM记忆突触可塑性研究
72nd Device Research Conference Pub Date : 2014-06-22 DOI: 10.1109/DRC.2014.6872334
N. Panwar, D. Kumar, N. Upadhyay, P. Arya, U. Ganguly, B. Rajendran
{"title":"Memristive synaptic plasticity in Pr0.7Ca0.3MnO3 RRAM by bio-mimetic programming","authors":"N. Panwar, D. Kumar, N. Upadhyay, P. Arya, U. Ganguly, B. Rajendran","doi":"10.1109/DRC.2014.6872334","DOIUrl":"https://doi.org/10.1109/DRC.2014.6872334","url":null,"abstract":"In this paper, the authors have demonstrated various forms of timing dependent plasticity in PCMO based RRAM devices using very simple programming pulses leveraging its memristive characteristics. Thanks to the intrinsic rectifying nature of their devices in the ON state, they have also shown that our synapse circuit does not require a current-limiting bipolar diode to prevent parasitic programming. These devices thus can be integrated in cross-bar arrays to build neuromorphic systems capable of performing a wide variety of supervised and unsupervised learning tasks.","PeriodicalId":293780,"journal":{"name":"72nd Device Research Conference","volume":"232 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114932925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Cryogenic implantation for source/drain junctions in Ge p-channel (Fin)FETs Ge p沟道(Fin) fet源极/漏极低温注入
72nd Device Research Conference Pub Date : 2014-06-22 DOI: 10.1109/DRC.2014.6872384
P. Bhatt, P. Swarnkar, S. Mittal, F. Basheer, C. Thomidis, C. Hatem, B. Colombeau, N. Variam, A. Nainani, S. Lodha
{"title":"Cryogenic implantation for source/drain junctions in Ge p-channel (Fin)FETs","authors":"P. Bhatt, P. Swarnkar, S. Mittal, F. Basheer, C. Thomidis, C. Hatem, B. Colombeau, N. Variam, A. Nainani, S. Lodha","doi":"10.1109/DRC.2014.6872384","DOIUrl":"https://doi.org/10.1109/DRC.2014.6872384","url":null,"abstract":"We demonstrate record boron activation >4×10<sup>20</sup>cm<sup>-3</sup> and contact resistivity of 1.7×10<sup>-8</sup>Ω-cm<sup>2</sup> on p<sup>+</sup>-Ge using a single boron implantation process step at cryogenic temperature followed by a low temperature (400<sup>o</sup>C) activation anneal. Unlike RT and hot (400<sup>o</sup>C) implantation, cryogenic implantation also gives shallower junctions (maintaining lower R<sub>sh</sub>) and higher I<sub>ON</sub>/I<sub>OFF</sub> ratio. Fin TEM and electrical data as well as device simulations for cryogenic, low energy BF<sub>2</sub> implanted epitaxial Ge fins indicate significant and scalable improvement in dopant activation vs room temperature implantation demonstrating feasibility of cryogenic implants for source/drain extensions of future 3D Ge channel p-FinFETs.","PeriodicalId":293780,"journal":{"name":"72nd Device Research Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125510894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Improved device isolation in AlGaN/GaN HEMTs on Si by heavy Kr+ Ion implantation 重Kr+离子注入提高硅基上AlGaN/GaN hemt的器件隔离
72nd Device Research Conference Pub Date : 2014-06-22 DOI: 10.1109/DRC.2014.6872324
S. Arulkumaran, G. Ng, K. Ranjan, G. Z. Saw, P. Murmu, J. Kennedy
{"title":"Improved device isolation in AlGaN/GaN HEMTs on Si by heavy Kr+ Ion implantation","authors":"S. Arulkumaran, G. Ng, K. Ranjan, G. Z. Saw, P. Murmu, J. Kennedy","doi":"10.1109/DRC.2014.6872324","DOIUrl":"https://doi.org/10.1109/DRC.2014.6872324","url":null,"abstract":"GaN high-electron-mobility transistor (HEMT) based technology demonstrated excellent high-frequency, high microwave power and power switching device applications that exceeded the existing Si technology limits. Inter device isolation of GaN-based HEMTs are typically achieved with either plasma mesa etching or ion implantation. The advantage for the ion implantation-based isolation approach is that it can offer device planarity and thus improve the fabrication yield. In addition, the planarity will avoid the gate from touching the 2DEG channel at the mesa-sidewall thus reduces the gate leakage current. For device isolation, different ion species (N+, O+, Ar+, Fe+ and Zn+) have been utilized for AlGaN/GaN HEMTs [1-5]. Except Fe+, no ion species have been proven to maintain the high resistivity of the the GaN buffer layer after high-temperature annealing. Recently, Umeda et al. reported thermally stable device isolation by Fe+ implantation [5]. However, Fe+-ions may create deep levels. In this work, we have selected inert Kr+-ions which can provide heavy damage to the crystal lattice. As Kr+ has ~2×, ~1.5× and 1.2× heavier atomic mass than Ar+, Fe+, and Zn+ ions, respectively. it is expected that the heavy Kr+-ion induced lattice damages/disorders will be hard to recover completely by high-temperature thermal annealing. To investigate the thermal stability of Kr+ implant-isolation, we have investigated thermal stability of implant-isolated samples by isochronal annealing process. To-date, there are also very few reports on the effect of the blocking voltage of implant-isolated AlGaN/GaN HEMT structures with SiN passivation [2], which has significant impact on their high breakdown voltage characteristics. Hence, in this work, we have also investigated the influence of SiN passivation in the device isolation current (i.e. buffer leakage current, Ibuff) on implant-isolated and mesa-isolated devices.","PeriodicalId":293780,"journal":{"name":"72nd Device Research Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116982085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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