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1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)最新文献

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Pattern design optimizing for GAT type power bipolar transistors GAT型功率双极晶体管的图案设计优化
1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105) Pub Date : 1998-10-21 DOI: 10.1109/ICSICT.1998.785832
Kang Baowei, Wang Zhe, Wu Yu, Cheng Xu
{"title":"Pattern design optimizing for GAT type power bipolar transistors","authors":"Kang Baowei, Wang Zhe, Wu Yu, Cheng Xu","doi":"10.1109/ICSICT.1998.785832","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785832","url":null,"abstract":"In this paper, the experimental results of planar pattern design optimizing aimed at current rating improvement for GAT type high-voltage high-speed power bipolar transistors are reported. These results show that the presently proposed pattern design with the base and emitter stripes intersected, obliquely and the base contacts arranged in island arrays is superior to that published by the inventor of GAT. The current rating is improved by 80%, while the switching fall time is reduced by 1/4.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"166 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126594664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Self-heating effect in SOI MOSFETs SOI mosfet的自热效应
1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105) Pub Date : 1998-10-21 DOI: 10.1109/ICSICT.1998.785951
S. Zimin, Liu Litian, L. Zhijian
{"title":"Self-heating effect in SOI MOSFETs","authors":"S. Zimin, Liu Litian, L. Zhijian","doi":"10.1109/ICSICT.1998.785951","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785951","url":null,"abstract":"Self-heating effect in SOI MOSFETs affects the carrier mobility, SOI MOSFETs threshold voltage and the band gap of silicon in channel. The mechanism of heat generation and heat dissipation in SOI MOSFETs is analyzed in this paper on the basis of which a simple self-heating effect model is established. The model introduces only one factor related with self-heating effect whose value can be easily determined according to the device structure parameters. The model is also verified experimentally.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125244197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
The design and program of a practical IC-CAM system 一个实用的集成电路凸轮系统的设计与程序设计
1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105) Pub Date : 1998-10-21 DOI: 10.1109/ICSICT.1998.785799
Zhan Guo, Xiaohua Kong, Cailan Xiang
{"title":"The design and program of a practical IC-CAM system","authors":"Zhan Guo, Xiaohua Kong, Cailan Xiang","doi":"10.1109/ICSICT.1998.785799","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785799","url":null,"abstract":"This paper focuses on a practical Integrated Circuit Computer Aided Manufacturing (IC-CAM). The system manages a complex IC fabrication procedure on three levels. It not only has the capability of flexible product dispatching and tracing, but can also schedule manufacture by order. By offering considerable charts and graphics, it provides real-time quality control. The design and programming of IC-CAM are discussed.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124771032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Technology of double side exposure and bonding for fabrication of accelerometer 加速度计双面曝光及粘接技术
1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105) Pub Date : 1998-10-21 DOI: 10.1109/ICSICT.1998.786524
Taiping Zhang, Ting Li, Ke-Qiang Deng
{"title":"Technology of double side exposure and bonding for fabrication of accelerometer","authors":"Taiping Zhang, Ting Li, Ke-Qiang Deng","doi":"10.1109/ICSICT.1998.786524","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.786524","url":null,"abstract":"The authors use double sided exposure and bonding and deep etching to fabricate accelerometers and gyroscopes. The technology is based on MEMS processing. The sensor testing is presented.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123353401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An optimization design of CMOS buffer using RSM technique 基于RSM技术的CMOS缓冲器优化设计
1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105) Pub Date : 1998-10-21 DOI: 10.1109/ICSICT.1998.785926
Xuewen Gan, Hailan Zhu
{"title":"An optimization design of CMOS buffer using RSM technique","authors":"Xuewen Gan, Hailan Zhu","doi":"10.1109/ICSICT.1998.785926","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785926","url":null,"abstract":"This paper presents an optimization design method for a CMOS buffer. A model equation for CMOS buffer delay time has been derived using the RSM experiment design technique. An optimization was then performed by means of the equations of the delay time and silicon area to obtain the optimum number of stages and the size scale factor for the CMOS buffer, which meets the requirement of delay time while having the minimum area, or achieving the minimum delay time with acceptable area. The optimization design method and the related software can also be used for other problems.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126396786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of a high speed 12-bit subranging A/D converter 高速12位分位a /D转换器的设计
1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105) Pub Date : 1998-10-21 DOI: 10.1109/ICSICT.1998.785903
Wang Ruoxu
{"title":"Design of a high speed 12-bit subranging A/D converter","authors":"Wang Ruoxu","doi":"10.1109/ICSICT.1998.785903","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785903","url":null,"abstract":"A high-speed 12-bit subranging analog-to-digital converter (ADC) is presented in the paper. Adapted in the circuit is a 3-stage subranging architecture of \"3-bit+3-bit+8-bit\", in which the 8-bit ADC is a folding and interpolating ADC, and the error correction is accomplished by analog correction and digital encoding. For fabrication techniques, the 2 /spl mu/m design rule, polysilicon-gate BiCMOS process, laser trimmed SiCr thin film resistor network and double metal routing are employed. SPICE simulation shows a 3 MHz sampling rate has been achieved at /spl plusmn/5 V power supply.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120957364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Characterisation of low-stress LPCVD silicon nitride in high frequency BJT's with self-aligned metallization 自对准金属化高频BJT低应力LPCVD氮化硅的表征
1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105) Pub Date : 1998-10-21 DOI: 10.1109/ICSICT.1998.785810
H. Zeijl, L. Nanver
{"title":"Characterisation of low-stress LPCVD silicon nitride in high frequency BJT's with self-aligned metallization","authors":"H. Zeijl, L. Nanver","doi":"10.1109/ICSICT.1998.785810","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785810","url":null,"abstract":"In the self-aligned metallization process, a metal base contact is self-aligned to the emitter by using free-standing silicon nitride spacers directly on the silicon. Low-stress silicon nitride (SiN/sub x/) is electrically characterized for use as a spacer material in this process. A comparison is also made to stoichiometric Si/sub 3/N/sub 4/ for which mechanical stress related problems can in some cases reduce the device yield. Overall good device characteristics and yield are obtained with the SiN/sub x/ spacers.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130735699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Several reliability related issues for flip-chip packaging 倒装芯片封装的几个可靠性问题
1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105) Pub Date : 1998-10-21 DOI: 10.1109/ICSICT.1998.785943
Sheng Liu, Jianjun Wang, Z. Qian
{"title":"Several reliability related issues for flip-chip packaging","authors":"Sheng Liu, Jianjun Wang, Z. Qian","doi":"10.1109/ICSICT.1998.785943","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785943","url":null,"abstract":"In this paper, several reliability-related mechanics problems in flip-chip packages are discussed. These problems include failure modes (cracking and delamination) and prevention, underfill selection and design, board design effect of processing induced defects (settling effect, incomplete fill, debonding), ball pitch effect, solder joint fatigue, and reliability of conductive epoxy.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131234309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Breakthrough to the "Silicon limit" of power devices 突破功率器件的“硅极限”
1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105) Pub Date : 1998-10-21 DOI: 10.1109/ICSICT.1998.785827
Xingbi Chen
{"title":"Breakthrough to the \"Silicon limit\" of power devices","authors":"Xingbi Chen","doi":"10.1109/ICSICT.1998.785827","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785827","url":null,"abstract":"The results of some new developments in voltage sustaining structures for both vertical and lateral power devices are presented. A figure of merit is defined for characterising the devices, show that they are far superior to those of prior art.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134361917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A new half-flash architecture for high speed video ADC 一种用于高速视频ADC的新型半闪存架构
1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105) Pub Date : 1998-10-21 DOI: 10.1109/ICSICT.1998.785900
Shi Yin, Li Shizu, Ronghua Zhu, Shoujue Wang
{"title":"A new half-flash architecture for high speed video ADC","authors":"Shi Yin, Li Shizu, Ronghua Zhu, Shoujue Wang","doi":"10.1109/ICSICT.1998.785900","DOIUrl":"https://doi.org/10.1109/ICSICT.1998.785900","url":null,"abstract":"In this paper a new half-flash architecture for high speed video ADC is presented. Based on a high speed single-way analog switch circuit, this architecture effectively reduces the number of elements. At the same time no sacrifice of speed is needed compared with the normal half-flash structure.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"118 1-2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134395735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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