高速12位分位a /D转换器的设计

1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105) Pub Date : 1998-10-21 DOI:10.1109/ICSICT.1998.785903

Wang Ruoxu

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引用次数: 3

摘要

介绍了一种高速12位分位模数转换器(ADC)。电路采用“3-bit+3-bit+8-bit”的三级分容架构，其中8-bit ADC为折叠插值ADC，纠错通过模拟校正和数字编码来完成。在制作工艺上，采用了2 /spl μ m设计原则、多晶硅栅极BiCMOS工艺、激光修整SiCr薄膜电阻网络和双金属布线。SPICE仿真表明，在/spl plusmn/ 5v电源下，采样率达到了3mhz。

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Design of a high speed 12-bit subranging A/D converter

A high-speed 12-bit subranging analog-to-digital converter (ADC) is presented in the paper. Adapted in the circuit is a 3-stage subranging architecture of "3-bit+3-bit+8-bit", in which the 8-bit ADC is a folding and interpolating ADC, and the error correction is accomplished by analog correction and digital encoding. For fabrication techniques, the 2 /spl mu/m design rule, polysilicon-gate BiCMOS process, laser trimmed SiCr thin film resistor network and double metal routing are employed. SPICE simulation shows a 3 MHz sampling rate has been achieved at /spl plusmn/5 V power supply.

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1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)

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