An optimization design of CMOS buffer using RSM technique

Abstract

This paper presents an optimization design method for a CMOS buffer. A model equation for CMOS buffer delay time has been derived using the RSM experiment design technique. An optimization was then performed by means of the equations of the delay time and silicon area to obtain the optimum number of stages and the size scale factor for the CMOS buffer, which meets the requirement of delay time while having the minimum area, or achieving the minimum delay time with acceptable area. The optimization design method and the related software can also be used for other problems.