Design of a high speed 12-bit subranging A/D converter

Abstract

A high-speed 12-bit subranging analog-to-digital converter (ADC) is presented in the paper. Adapted in the circuit is a 3-stage subranging architecture of "3-bit+3-bit+8-bit", in which the 8-bit ADC is a folding and interpolating ADC, and the error correction is accomplished by analog correction and digital encoding. For fabrication techniques, the 2 /spl mu/m design rule, polysilicon-gate BiCMOS process, laser trimmed SiCr thin film resistor network and double metal routing are employed. SPICE simulation shows a 3 MHz sampling rate has been achieved at /spl plusmn/5 V power supply.