2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)最新文献_第2页

A 76-Gbit/s 265-GHz CMOS Receiver 一个76 gbit /s的265 ghz CMOS接收器

2021 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2021-11-07 DOI: 10.1109/A-SSCC53895.2021.9634780

S. Hara, R. Dong, Sangyeop Lee, K. Takano, Naoya Toshida, S. Tanoi, Tatsuo Hagino, M. Mubarak, N. Sekine, I. Watanabe, A. Kasamatsu, K. Sakakibara, Shunichi Kubo, Satoshi Miura, Y. Umeda, T. Yoshida, S. Amakawa, M. Fujishima

引用次数: 7

245/243GHz, 9.2/10.5dBm Saturated Output Power, 4.6/2.8% PAE, and 28/26dB Gain Power Amplifiers in 65nm CMOS Adopting 2-and 4-way Power Combining 245/243GHz, 9.2/10.5dBm饱和输出功率，4.6/2.8% PAE, 28/26dB增益的65nm CMOS功率放大器，采用2路和4路功率组合

2021 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2021-11-07 DOI: 10.1109/A-SSCC53895.2021.9634180

Byeonghun Yun, Dae-Woong Park, Kyung-Sik Choi, Ho-Jin Song, Sang-Gug Lee

引用次数: 0

A 2.7-Gb/s Multiplexed-DLL-Based CDR Circuit for ±10% Clock-Embedded Spread-Spectrum Modulation Depth 一种基于2.7 gb /s多路dll的±10%时钟嵌入式扩频调制深度的CDR电路

2021 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2021-11-07 DOI: 10.1109/A-SSCC53895.2021.9634705

Yen-Kuei Lu, Miao-Shan Li, Ching-Yuan Yang, Chin-Lung Lin

{"title":"A 2.7-Gb/s Multiplexed-DLL-Based CDR Circuit for ±10% Clock-Embedded Spread-Spectrum Modulation Depth","authors":"Yen-Kuei Lu, Miao-Shan Li, Ching-Yuan Yang, Chin-Lung Lin","doi":"10.1109/A-SSCC53895.2021.9634705","DOIUrl":"https://doi.org/10.1109/A-SSCC53895.2021.9634705","url":null,"abstract":"Because Electromagnetic interference (EMI) stems from system clocks, it can be most efficiently and economically reduced with the use of spread spectrum clock (SSC) oscillators. To reduce more EMI, such as intra-panel interfaces, the energy of the processed signal after spread-spectrum modulation is spread over a wider bandwidth [1–3]. As a result, it will encounter some problems while employing the traditional type-2 PLL-based clock and data recovery (CDR) for phase-tracking SSC operation. Firstly, a wide spread-spectrum modulation depth with an increased frequency ramp makes the PLL system easily losing phase lock. Secondly, to catch up with the frequency ramp of the spread-spectrum signal, the system bandwidth must be increased, resulting in stability problems. Thirdly, considering the CDR recovering the data with the effect of spread-spectrum signal, the jitter tolerance of the system becomes worse. In order to overcome the above-mentioned problems, this work adopts the final value theorem to analyze the steady-state phase error of the system for ± 10% spread-spectrum modulation depth and modulation frequency of 200 kHz.","PeriodicalId":286139,"journal":{"name":"2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116866824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 70mW Indirect Time-of-Flight Image Sensor with Depth Dynamic Range Enhancement and Fixed Depth Noise Compensation 具有深度动态范围增强和固定深度噪声补偿的70mW间接飞行时间图像传感器

2021 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2021-11-07 DOI: 10.1109/A-SSCC53895.2021.9634817

Canxing Piao, Yeonsoo Ahn, Donguk Kim, Jihoon Park, Jubin Kang, Minseok Shin, Kangbong Seo, Seong-Jin Kim, J. Chun, Jaehyuk Choi

{"title":"A 70mW Indirect Time-of-Flight Image Sensor with Depth Dynamic Range Enhancement and Fixed Depth Noise Compensation","authors":"Canxing Piao, Yeonsoo Ahn, Donguk Kim, Jihoon Park, Jubin Kang, Minseok Shin, Kangbong Seo, Seong-Jin Kim, J. Chun, Jaehyuk Choi","doi":"10.1109/A-SSCC53895.2021.9634817","DOIUrl":"https://doi.org/10.1109/A-SSCC53895.2021.9634817","url":null,"abstract":"Indirect time-of-flight (iTOF) is a 3D depth-sensing technology that provides the distance to the object by measuring the phase difference of emitted and reflected waves of light. Usually, iTOF sensors consume power over 200 mW owing to high frequency modulation, which prevents them from the application to the energy limited wearable devices for VR/AR. To minimize column fixed depth noise (FDN), the TX driver typically has a double-sided clock tree that provides TX signals from both the left and the right sides of the pixel array [1], [2]. However, the double-sided driver consumes significant power even though the column FDN is still present. Moreover, the clock tree generates a huge peak current to induce depth noise. Some sensors employed a clock chain to distribute the peak current [3], [4]. Because the chain induces inherent row FDN, they used a DLL [3] or two opposite-directional chains [4] for the post compensation. However, these schemes still have column FDN, power consumption from the double-sided driver, and PVT variation. Another important issue is a limited depth dynamic range (DDR) because reflected light power falls along with the squared distance. Saturation occurs for short range (SR) whereas noise overwhelms signal for long range (LR). For the WDDR, two or multiple shots of images should be synthesized while consuming additional power.","PeriodicalId":286139,"journal":{"name":"2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125953743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A 33.5-37.5 GHz 4-Element Phased-Array Transceiver Front-End with High-Accuracy Low-Variation 6-bit Resolution 360° Phase Shift and 0~31.5 dB Gain Control in 65 nm CMOS 一种高精度低变化6位分辨率360°相移和0~31.5 dB增益控制的65 nm CMOS 33.5-37.5 GHz 4元相控阵收发器前端

2021 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2021-11-07 DOI: 10.1109/A-SSCC53895.2021.9634826

Pingda Guan, Haikun Jia, W. Deng, Zhihua Wang, B. Chi

{"title":"A 33.5-37.5 GHz 4-Element Phased-Array Transceiver Front-End with High-Accuracy Low-Variation 6-bit Resolution 360° Phase Shift and 0~31.5 dB Gain Control in 65 nm CMOS","authors":"Pingda Guan, Haikun Jia, W. Deng, Zhihua Wang, B. Chi","doi":"10.1109/A-SSCC53895.2021.9634826","DOIUrl":"https://doi.org/10.1109/A-SSCC53895.2021.9634826","url":null,"abstract":"Millimeter-wave (mm-wave) phased-arrays for 5G communication, radar, and satellite communication systems have obtained ever-increasing attention. Power amplifiers (PAs) are one of the most critical components in phased-array front-ends (FEs). High output power is desired to support long-range communications and radar detection. Another critical component is the phase and gain controller that enables electric beam scanning. High accuracy, fine resolution, and orthogonality of phase and gain control are vital to support precise beamforming and improve usability. In this paper, we present a 33.5-37.5 GHz 4-element phased-array transceiver (TRX) FE with power combining PAs and hybrid architecture phase/gain controllers in 65 nm CMOS, which achieves (1) $P_{text {sat }}$ of $19.8 dBm$ and $P_{1 dB}$ of $17.2 dBm$ per element, (2) 6-bit 360° phase shift range with RMS phase error less than 2° and gain variation less than $pm 2 dB,(3)$ and 6 -bit 0-31.5 dB gain control range with RMS gain error less than $0.16 dB$ and phase variation less than ±3°.","PeriodicalId":286139,"journal":{"name":"2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129872819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A 0.79–1.16-GHz Synthesizable Fractional-N PLL Using DTC-Based Multi-Stage Injection with Dithering-Assisted Local Skew Calibration Achieving −232.8-dB FoMref 基于dtc的多级注入与抖动辅助的局部倾斜校准实现−232.8 db的0.79 - 1.16 ghz可合成分数n锁相环

2021 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2021-11-07 DOI: 10.1109/A-SSCC53895.2021.9634799

Zule Xu

引用次数: 1

A 7.9-14.3GHz -243.3dB FoMT Sub-Sampling PLL with Transformer-Based Dual-Mode VCO in 40nm CMOS 基于变压器的40nm CMOS双模压控振荡器7.9-14.3GHz -243.3dB fmt子采样锁相环

2021 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2021-11-07 DOI: 10.1109/A-SSCC53895.2021.9634839

Yizhuo Wang, T. Zou, Bowen Chen, Shujiang Ji, Chaoxuan Zhang, N. Yan

引用次数: 3

A 99.5dB-DR 5kHz-BW Closed-Loop Neural-Recording IC based on Continuous-Time Dynamic-Zoom ΔΣ ADC with Automatic AFE-Gain Control 基于自动afe增益控制的连续动态变焦ΔΣ ADC的99.5dB-DR 5kHz-BW闭环神经记录IC

2021 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2021-11-07 DOI: 10.1109/A-SSCC53895.2021.9634824

Yoontae Jung, Soon-Jae Kweon, Hyuntak Jeon, Taeju Lee, Injun Choi, Kyeongwon Jeong, Mi Kyung Kim, H. J. Lee, S. Ha, M. Je

{"title":"A 99.5dB-DR 5kHz-BW Closed-Loop Neural-Recording IC based on Continuous-Time Dynamic-Zoom ΔΣ ADC with Automatic AFE-Gain Control","authors":"Yoontae Jung, Soon-Jae Kweon, Hyuntak Jeon, Taeju Lee, Injun Choi, Kyeongwon Jeong, Mi Kyung Kim, H. J. Lee, S. Ha, M. Je","doi":"10.1109/A-SSCC53895.2021.9634824","DOIUrl":"https://doi.org/10.1109/A-SSCC53895.2021.9634824","url":null,"abstract":"Neural-recording ICs have been a key tool to unravel the mystery of the human brain and find treatments for various neurological diseases. Since neural signals inherently have a small amplitude and suffer from environmental interferences, conventional neural recording circuits have been mainly designed for low noise, high CMRR, and low power, using the structure with a high-gain amplifier and a low-resolution ADC [1] (Fig. 1). With the advent of closed-loop neurotherapeutics, stimulation artifacts have been a notorious obstacle in neural recording. To tackle this issue, a direct-conversion structure has been widely used due to its wide dynamic range [3] –[7]. However, the structure could not meet the bandwidth (BW) requirement of 5kHz and the input-referred noise (IRN) requirement of $7 mu V_{rms}$ simultaneously. In this paper, we present a closed-loop neural-recording IC using an adaptive automatic gain controller (AGC) and continuous-time dynamic-zoom $Delta Sigma$ ADC (CT-Zoom-ADC). By combining the AGC and CT-Zoom-ADC, the IRN performance is improved to $6.1 mu V_{rms}$ at 5kHz BW, and the saturation issue of the conventional amplifier-based recording structure is alleviated. Also, the recording IC can rapidly recover the signal from transient artifacts thanks to the digital auto-ranging block (DAR).","PeriodicalId":286139,"journal":{"name":"2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125106812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A 48Gb/s 2.4pJ/b PAM-4 Baud-Rate Digital CDR with Stochastic Phase Detection Technique in 40nm CMOS 基于随机相位检测技术的48Gb/s 2.4pJ/b PAM-4波特率数字CDR

2021 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2021-11-07 DOI: 10.1109/A-SSCC53895.2021.9634737

Haram Ju, Kwangho Lee, W. Jung, D. Jeong

{"title":"A 48Gb/s 2.4pJ/b PAM-4 Baud-Rate Digital CDR with Stochastic Phase Detection Technique in 40nm CMOS","authors":"Haram Ju, Kwangho Lee, W. Jung, D. Jeong","doi":"10.1109/A-SSCC53895.2021.9634737","DOIUrl":"https://doi.org/10.1109/A-SSCC53895.2021.9634737","url":null,"abstract":"Since oversampling-based clock and data recovery (CDR) requires additional clocking power [1–2], Baud-rate CDR draws attraction in PAM-4 receivers (RXs) recently. The most popular PAM-4 Baud-rate CDR utilizes Mueller-Müller CDR, which requires an analog-to-digital converter (ADC) [3–4]. However, these ADC-based PAM-4 CDR designs are power-hungry due to the use of high-speed and high-resolution ADCs and bulky digital back-ends including decision-feedback equalizers (DFEs) and feed-forward equalizers (FFEs) in the digital domain. For simplicity, a sign-sign Mueller-Müller phase detector (SS-MMPD) was presented that employed two voltage references instead of using an ADC [5]. Meanwhile, machine learning (ML)-inspired design procedure of the stochastic phase-frequency detector (SPFD) is introduced for a 2x-oversampling referenceless CDR [6]. This paper extends the design procedure to find the optimal weights for the PAM-4 Baud-rate phase detector (PD). As a result, the proposed stochastic phase detector (SPD) achieves an optimal phase-locking capability that maximizes the PAM-4 vertical eye opening (VEO) compared to the conventional logical approaches.","PeriodicalId":286139,"journal":{"name":"2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125226914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A process scalable voltage-reference-free temperature sensor utilizing MOSFET threshold voltage variation 一种利用MOSFET阈值电压变化的过程可扩展无电压参考温度传感器

2021 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2021-11-07 DOI: 10.1109/A-SSCC53895.2021.9634727

Shogo Harada, Mahfuzul Islam, T. Hisakado, O. Wada

引用次数: 2