A 48Gb/s 2.4pJ/b PAM-4 Baud-Rate Digital CDR with Stochastic Phase Detection Technique in 40nm CMOS

Abstract

Since oversampling-based clock and data recovery (CDR) requires additional clocking power [1–2], Baud-rate CDR draws attraction in PAM-4 receivers (RXs) recently. The most popular PAM-4 Baud-rate CDR utilizes Mueller-Müller CDR, which requires an analog-to-digital converter (ADC) [3–4]. However, these ADC-based PAM-4 CDR designs are power-hungry due to the use of high-speed and high-resolution ADCs and bulky digital back-ends including decision-feedback equalizers (DFEs) and feed-forward equalizers (FFEs) in the digital domain. For simplicity, a sign-sign Mueller-Müller phase detector (SS-MMPD) was presented that employed two voltage references instead of using an ADC [5]. Meanwhile, machine learning (ML)-inspired design procedure of the stochastic phase-frequency detector (SPFD) is introduced for a 2x-oversampling referenceless CDR [6]. This paper extends the design procedure to find the optimal weights for the PAM-4 Baud-rate phase detector (PD). As a result, the proposed stochastic phase detector (SPD) achieves an optimal phase-locking capability that maximizes the PAM-4 vertical eye opening (VEO) compared to the conventional logical approaches.