2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)最新文献

RAODAT: An Energy-Efficient Reconfigurable AI-based Object Detection and Tracking Processor with Online Learning RAODAT:一种具有在线学习功能的高能效可重构人工智能目标检测与跟踪处理器

2021 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2021-11-07 DOI: 10.1109/A-SSCC53895.2021.9634785

Yuchuan Gong, Qingsong Liu, Luying Que, Conghan Jia, Jiahui Huang, Ye Liu, Jiayan Gan, Yuxiang Xie, Yong Zhou, Lili Liu, Xiaoqiang Xiang, L. Chang, Jun Zhou

{"title":"RAODAT: An Energy-Efficient Reconfigurable AI-based Object Detection and Tracking Processor with Online Learning","authors":"Yuchuan Gong, Qingsong Liu, Luying Que, Conghan Jia, Jiahui Huang, Ye Liu, Jiayan Gan, Yuxiang Xie, Yong Zhou, Lili Liu, Xiaoqiang Xiang, L. Chang, Jun Zhou","doi":"10.1109/A-SSCC53895.2021.9634785","DOIUrl":"https://doi.org/10.1109/A-SSCC53895.2021.9634785","url":null,"abstract":"Smart robots (e.g. drones) for object detection & tracking demand for embedded intelligent processors. Neural network (NN) processors have been designed to accelerate NN for pattern recognition [1] [2]. However, these designs lack special processing engines for object detection & tracking such as bounding box (bbox) calculation and selection. Also, their architectures are designed for general AI tasks resulting in redundancy/inefficiency in performing object detection & tracking. An object detection processor has been proposed previously [3], but it only supports specific detection NN and does not support object tracking. Object tracking processors have also been proposed [4] [5], but these designs do not support object detection and thus cannot be used for object search. This paper presents RAODAT, which to the best of our knowledge is the first reconfigurable AI-based object detection and tracking processor with online learning. It has three key features: 1) An object detection & tracking architecture with reconfigurable NN and detection/tracking engines for programmable object detection & tracking tasks, 2) An object learning architecture with shared NN inference/learning engine and automatic label generation engine to support object tracking with online learning, 3) Layer- & stride-aware computing techniques to improve the NN computation efficiency.","PeriodicalId":286139,"journal":{"name":"2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126987010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A 4.57 μW@120fps Vision System of Sensing with Computing for BNN-Based Perception Applications 基于bnn的感知应用4.57 μW@120fps计算传感视觉系统

2021 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2021-11-07 DOI: 10.1109/A-SSCC53895.2021.9634759

Han Xu, Zheyu Liu, Ziwei Li, Erxiang Ren, Maimaiti Nazhamati, F. Qiao, Li Luo, Qi Wei, Xinjun Liu, Huazhong Yang

{"title":"A 4.57 μW@120fps Vision System of Sensing with Computing for BNN-Based Perception Applications","authors":"Han Xu, Zheyu Liu, Ziwei Li, Erxiang Ren, Maimaiti Nazhamati, F. Qiao, Li Luo, Qi Wei, Xinjun Liu, Huazhong Yang","doi":"10.1109/A-SSCC53895.2021.9634759","DOIUrl":"https://doi.org/10.1109/A-SSCC53895.2021.9634759","url":null,"abstract":"In AIoT era, intelligent vision perception systems are widely deployed in edges. As shown in Fig. 1, due to limited energy budget, terminal devices usually adopt hierarchical processing architecture. A coarse object detection algorithm runs in always-on mode, and gets ready to trigger subsequent complex algorithms for precise recognition or segmentation. In conventional digital vision processing frameworks, light-induced photocurrents must be transformed to voltage ${mathrm {(I_{ph}-to-V)}}$, converted to digital signals (A-to-D), transferred on-board to processors and exchanged between memory and processing elements. Smart vision chips provide promising solutions for cutting down these power overheads, such as placing analog processing circuits near the pixel array [2], customizing the analog-to-digital converter (ADC) which is capable of convolution [3] or adding processing circuits deeply into pixels to perform in-sensor current-domain MAC operations [4]. However, the photocurrent conversion ${mathrm {(I_{ph}-to-V)}}$ circuits are still reserved in those works; besides, they could only complete 1st-layer convolution for low-level features extraction, and are unable to process subsequent layers for end-to-end perception tasks, which limits the processing capability with small CNN model. Additionally, systems that implement whole CNN algorithms are also proposed by integrating CIS with an analog processor in one chip [5] or stacking a CIS chip with a digital processor chip [6]. But power overheads on data transmission and memory access are still unsolved because these designs separate sensing and computing, and adopt conventional Von Neumann architecture with much memory access.","PeriodicalId":286139,"journal":{"name":"2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115187423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

CIM-SECDED: A 40nm 64Kb Compute In-Memory RRAM Macro with ECC Enabling Reliable Operation CIM-SECDED:具有ECC的40nm 64Kb计算内存RRAM宏，可实现可靠操作

2021 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2021-11-07 DOI: 10.1109/A-SSCC53895.2021.9634742

Brian Crafton, S. Spetalnick, Jong-Hyeok Yoon, Wei Wu, Carlos Tokunaga, V. De, A. Raychowdhury

{"title":"CIM-SECDED: A 40nm 64Kb Compute In-Memory RRAM Macro with ECC Enabling Reliable Operation","authors":"Brian Crafton, S. Spetalnick, Jong-Hyeok Yoon, Wei Wu, Carlos Tokunaga, V. De, A. Raychowdhury","doi":"10.1109/A-SSCC53895.2021.9634742","DOIUrl":"https://doi.org/10.1109/A-SSCC53895.2021.9634742","url":null,"abstract":"Resistive RAM (RRAM) is a promising candidate for compute in-memory (CIM) applications owing to its natural multiply-and-accumulate structure in a 1T-1R bitcell, high-bit density, non-volatility, and voltage and process compatibility. These properties seek to advance applications such as AI with higher throughput and bit-density. However, due to process, temperature, and write-to-write variations the resistive state of each RRAM undergoes both spatial and temporal variations. Significant effort has been made to reduce the impact of device variation using iterative write verify (IWV) or training-aware approaches [1]. Unfortunately, traditional ECC is not compatible with CIM when multiple cells are read simultaneously on the same bitline. To address this issue at the circuit level, this paper presents a 64Kb RRAM macro in 40nm CMOS supporting SECDED (single error correction, double error detection) scheme compatible with CIM for any number of parallel row accesses. Compared to prior work, our results indicate that CIM-SECDED (1) improves bit error rate (BER) by up to $69.2 times $ for compute in-memory (2) relaxes the constraints on resistance variations and directly lowers IWV and write voltages. As a result, when applied to AI workloads we achieve (1) 24.4% (29.9%) accuracy improvement on the CIFAR10 (ImageNet) dataset (2) and consequently, improved endurance though lowering write voltage requirements [2].","PeriodicalId":286139,"journal":{"name":"2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122460282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

FPGA-Based Ordered Statistic Decoding Architecture for B5G/6G URLLC IIOT Networks 基于fpga的B5G/6G URLLC IIOT网络有序统计解码架构

2021 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2021-11-07 DOI: 10.1109/A-SSCC53895.2021.9634714

Changhyeon Kim, Dongyoung Rim, Jeongwon Choe, D. Kam, Giyoon Park, Seokki Kim, Youngjoo Lee

引用次数: 1

A 5-GHz 0.15-mm2 Collision Avoidable RFID Employing Complementary Pass-transistor Adiabatic Logic with an Inductively Connected External Antenna 采用互补通管绝热逻辑与电感连接外部天线的5 ghz 0.15 mm2可避免碰撞RFID

2021 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2021-11-07 DOI: 10.1109/A-SSCC53895.2021.9634815

Saito Shibata, Reiji Miura, Yoshiki Sawabe, K. Shiba, Atsutake Kosuge, M. Hamada, T. Kuroda

引用次数: 2

Auto-Calibration Technique for Current-Based Bandgap Voltage Reference 基于电流的带隙基准电压自动校准技术

2021 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2021-11-07 DOI: 10.1109/A-SSCC53895.2021.9634776

U. Chi-Wa, M. Law, C. Lam, R. Martins

引用次数: 1

A ± 20-ppm -50°C-105°C 1-µA 32.768-kHz Clock Generator with a System-HFXO-Assisted Background Calibration ±20 ppm -50°C-105°C 1-µA 32.768 khz时钟发生器，带有system - hfxo辅助背景校准

2021 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2021-11-07 DOI: 10.1109/A-SSCC53895.2021.9634827

Chun-Yu Lin, Yu-Wei Huang, Tsung-Hsien Lin

引用次数: 0

A 95% Peak Efficiency Modified KY (Boost) Converter for IoT with Continuous Flying Capacitor Charging in DCM DCM中连续飞行电容充电的物联网95%峰值效率改进KY (Boost)变换器

2021 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2021-11-07 DOI: 10.1109/A-SSCC53895.2021.9634724

Wen-Liang Zeng, Caolei Pan, C. Lam, Sai-Weng Sin, Chenchang Zhan, R. Martins

引用次数: 1

A 21Gb/s Duobinary Transceiver for GDDR interfaces with an Adaptive Equalizer 带有自适应均衡器的21Gb/s双二进制GDDR接口收发器

2021 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2021-11-07 DOI: 10.1109/A-SSCC53895.2021.9634179

Jae-Woo Park, Dong-Seok Kang, Injae Park, Minsu Park, Xuefan Jin, Kyu-Dong Hwang, Daehan Kwon, J. Chun

引用次数: 2

A-SSCC 2021 Cover Page A-SSCC 2021封面

2021 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2021-11-07 DOI: 10.1109/a-sscc53895.2021.9634726

引用次数: 0