带有自适应均衡器的21Gb/s双二进制GDDR接口收发器

2021 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2021-11-07 DOI:10.1109/A-SSCC53895.2021.9634179

Jae-Woo Park, Dong-Seok Kang, Injae Park, Minsu Park, Xuefan Jin, Kyu-Dong Hwang, Daehan Kwon, J. Chun

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引用次数: 2

摘要

采用28nm CMOS技术实现了图形双数据速率(GDDR)存储接口的双二进制收发器。在不牺牲电平失配比(RLM)的情况下，所提出的电压模式驱动器符合GDDR阻抗规范。四分之一速率时间交错连续逼近双二进制接收机降低了转发时钟频率，并使前端模拟均衡器的容性负载最小化。同时，提出了一种适用于二进制信令的均衡器自适应方案。该收发器在21 Gb/s下的误码率为10$^{-11}$，能效为1.62 mw /Gb/s。

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A 21Gb/s Duobinary Transceiver for GDDR interfaces with an Adaptive Equalizer

A duobinary transceiver for Graphics Double Data rate (GDDR) memory interfaces is implemented in a 28nm CMOS technology. The proposed voltage-mode driver complies with the GDDR impedance specifications without sacrificing the ratio of level mismatch (RLM). The quarter-rate time-interleaved successive approximation duobinary receiver reduces the forwarded clock frequency and minimizes the capacitive loading of the front-end analog equalizer. Also, an equalizer adaptation scheme applicable to duobinary signaling is proposed. The transceiver achieves a BER of 10$^{-11}$ at 21 Gb/s with 1.62-mW/Gb/s energy efficiency.

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2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)

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