A 21Gb/s Duobinary Transceiver for GDDR interfaces with an Adaptive Equalizer

Abstract

A duobinary transceiver for Graphics Double Data rate (GDDR) memory interfaces is implemented in a 28nm CMOS technology. The proposed voltage-mode driver complies with the GDDR impedance specifications without sacrificing the ratio of level mismatch (RLM). The quarter-rate time-interleaved successive approximation duobinary receiver reduces the forwarded clock frequency and minimizes the capacitive loading of the front-end analog equalizer. Also, an equalizer adaptation scheme applicable to duobinary signaling is proposed. The transceiver achieves a BER of 10$^{-11}$ at 21 Gb/s with 1.62-mW/Gb/s energy efficiency.