A 2.7-Gb/s Multiplexed-DLL-Based CDR Circuit for ±10% Clock-Embedded Spread-Spectrum Modulation Depth

Abstract

Because Electromagnetic interference (EMI) stems from system clocks, it can be most efficiently and economically reduced with the use of spread spectrum clock (SSC) oscillators. To reduce more EMI, such as intra-panel interfaces, the energy of the processed signal after spread-spectrum modulation is spread over a wider bandwidth [1–3]. As a result, it will encounter some problems while employing the traditional type-2 PLL-based clock and data recovery (CDR) for phase-tracking SSC operation. Firstly, a wide spread-spectrum modulation depth with an increased frequency ramp makes the PLL system easily losing phase lock. Secondly, to catch up with the frequency ramp of the spread-spectrum signal, the system bandwidth must be increased, resulting in stability problems. Thirdly, considering the CDR recovering the data with the effect of spread-spectrum signal, the jitter tolerance of the system becomes worse. In order to overcome the above-mentioned problems, this work adopts the final value theorem to analyze the steady-state phase error of the system for ± 10% spread-spectrum modulation depth and modulation frequency of 200 kHz.