A 0.79–1.16-GHz Synthesizable Fractional-N PLL Using DTC-Based Multi-Stage Injection with Dithering-Assisted Local Skew Calibration Achieving −232.8-dB FoMref

Phase-locked loops (PLLs) are imperative building blocks in wireless system-on-chips (SoCs) for modulation and clock generation. Their design and implementation typically take long time, especially when multiple PLLs are needed in a large-scale SoC. To reduce this time, synthesizable PLLs have been proposed using standard cells with automatic place-and-route (P&R) [1] –[5]. In these PLLs, ring digitally-controlled oscillators (DCOs) are employed whose high phase noises can be suppressed by edge injection [1] or multiplying-delay-locked loops (MDLLs) [2], [4], [5] (in the following context, the term “injection” is used for convenience). Although automatic P&R drastically reduces design and implementation time, it introduces unpredictable parasitic elements which degrade phase noise and spurs. The situation can even worsen in a fractional-N PLL where a digital-to-time converter (DTC) is involved, whose jitter and linearity are crucial but tend to be undermined by automatic P&R.