52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)最新文献_第2页

Shifting from 12-V to 42-V systems in automotive applications 在汽车应用中从12v系统转换到42v系统

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008344

K. Pandya, Klaus Pietrczak

引用次数: 0

A numerical study of the effect of die, die pad and die attach thicknesses on thin plastic packages 采用数值方法研究了模具、模具垫和模具附着厚度对薄塑料封装的影响

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008095

A. Tay, H. Zhu

{"title":"A numerical study of the effect of die, die pad and die attach thicknesses on thin plastic packages","authors":"A. Tay, H. Zhu","doi":"10.1109/ECTC.2002.1008095","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008095","url":null,"abstract":"In this paper, the effects of thickness of the die (t/sub d/), die-pad (t/sub p/) and die attach (t/sub a/) on delaminations in Thin Shrink Small Outline Plastic IC packages were studied. The effects of t/sub d/ and t/sub p/ on Crack I, II and III are individually investigated where Crack I lies in the pad-encapsulant interface, Crack II in the die-encapsulant interface and Crack III in the pad-die attach interface. A fracture mechanics approach was used to compute the strain energy release rate (ERR) at the crack tips. For the die attach thickness t/sub a/, only its effect on Crack III was investigated. According to the literature, the Young's Modulus E of the die attach has a great influence on delamination along the pad-die attach interface. Thus a full factorial analysis of die attach thickness (t/sub a/) and Young's Modulus E on Crack III crack tip energy release rate was also carried out. Among other things, it was found that increasing the thickness of the die increases the ERR of cracks at all three interfaces and increasing the thickness of die pad increases the ERR of Crack I and II. It was also found that a smaller Young's Modulus and a greater thickness of the die attach is a good design against propagation of Crack III.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122212204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Impact of ball via configurations on solder joint reliability in tape-based, chip-scale packages 在基于磁带的芯片级封装中，球孔结构对焊点可靠性的影响

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008301

B. Zahn

{"title":"Impact of ball via configurations on solder joint reliability in tape-based, chip-scale packages","authors":"B. Zahn","doi":"10.1109/ECTC.2002.1008301","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008301","url":null,"abstract":"Three-dimensional finite element analysis has been applied to determine the time-dependent solder joint fatigue response of a tape based chip-scale package under accelerated temperature cycling conditions (-40C to +125C, 15min ramps/15min dwells). The effects of differing ball via configurations due to variations in both package assembly and tape vendors were investigated, including the use of punched, etched, laser etched, and enhanced re-flow pad area vias. The solder structures accommodate the bulk of the plastic strain that is generated during accelerated temperature cycling due to the thermal expansion mismatch between the various materials that encompass the chip-scale package. Since plastic strain is a dominant parameter that influences low-cycle fatigue, it was used as a basis for evaluation of solder joint structural integrity. An extensively published and correlated solder joint fatigue life prediction methodology was incorporated by which finite element simulation results were translated into estimated cycles to failure. This study discusses the analysis methodologies as implemented in the ANSYS finite element simulation software tool.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128336505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 59

Digital and RF integration in system-on-a-package (SOP) 系统单包(SOP)中的数字和射频集成

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008164

V. Sundaram, Fuhan Liu, S. Dalmia, J. Hobbs, E. Matoglu, M. Davis, T. Nonaka, J. Laskar, Madhavan Swaminathan, George E. White, Rao Tummala

{"title":"Digital and RF integration in system-on-a-package (SOP)","authors":"V. Sundaram, Fuhan Liu, S. Dalmia, J. Hobbs, E. Matoglu, M. Davis, T. Nonaka, J. Laskar, Madhavan Swaminathan, George E. White, Rao Tummala","doi":"10.1109/ECTC.2002.1008164","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008164","url":null,"abstract":"The Packaging Research Center (PRC) is developing system-on-a-package (SOP) technology, as a complimentary alternative to SOC, as the fundamental building block for next generation convergent systems with computing, telecom and consumer capabilities with data and voice. Any systems of this nature have to provide not only high-speed digital, but also high bandwidth optical, analog, RF and perhaps MEMS functions. The SOP technology being pursued at PRC with embedded digital, optical and RF functions addresses this need, optimizing the IC and the package for functions, performance, cost, size and reliability. The PRC is developing this complimentary alternative to SOC using a three tier strategy consisting of fundamental research innovations, enabling technology developments and system-level testbeds. Individual digital, optical and RF testbeds have been developed to enable the integration of novel packaging technologies like embedded passive and optical components, high density global interconnections and wafer level flip-chip assembly. A phased system testbed is being evolved from these three testbeds to develop new SOP convergent system platforms for a digital/optical/RF system implementation. This paper summarizes the latest PRC accomplishments in the development of SOP baseline processes and system testbeds and updates the progress from basic research and technology integration to system testbeds for SOP.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129489943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

Performance evaluation of RF MEMS packages 射频MEMS封装的性能评估

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008229

L. Hwang, Li Li, J. Drye, S. Kuo

{"title":"Performance evaluation of RF MEMS packages","authors":"L. Hwang, Li Li, J. Drye, S. Kuo","doi":"10.1109/ECTC.2002.1008229","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008229","url":null,"abstract":"An RF switch made using MEMS (Micro Electro-Mechanical System) technology shows attractive electrical characteristics that are critically needed in the next generation low power consumption, high data rate RF wireless systems. In order to provide environmental protection and at the same time preserve electrical performance of the MEMS switch, an RF package must be carefully designed. For example, it is important for the RF package to maintain low insertion loss, low return loss, and high isolation between ports of the MEMS switches. In this paper, a methodology used to analyze: the electrical performance of packaged switches is described. Simulation results of two Kyocera ceramic packages are shown. Ansoft HFSS fullwave simulator was used to obtain the package and wire bond interconnect characteristics, and combined with either measured or simulated device characteristics. The results were compared with general system specifications. Wire bond profiles, which resemble those actually were used in the packages, were created in the simulation. The three-dimensional grounding system of the packages was also implemented in the simulation. Experimental validation using TRL on-board calibration and direct SOLT package probing were also completed.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130554709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

No-flow underfill process modeling and analysis for low cost, high throughput flip chip assembly 低成本、高通量倒装芯片组装的无流下填工艺建模与分析

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008290

Chunho Kim, D. Baldwin

{"title":"No-flow underfill process modeling and analysis for low cost, high throughput flip chip assembly","authors":"Chunho Kim, D. Baldwin","doi":"10.1109/ECTC.2002.1008290","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008290","url":null,"abstract":"No-flow underfill process has been widely accepted as a key technology to implement low-cost, high-throughput flip chip on board (FCOB) assembly because of the elimination of processing steps such as flux application, flux residue cleaning, capillary underfill flow and secondary thermal curing of the underfill. While feasibility tests for the low-cost, high-throughput flip chip assembly based on no-flow underfill over a wide range of flip chip configurations are underway, unfamiliar process defects that have not been observed in the conventional capillary flow process are newly emerging. Of those new process defects, \"chip floating\" over the board surface after chip placement process is a critical issue that may significantly impact process yield when process variables are not properly controlled. It was found that much of the yield losses observed post reflow is attributed to the \"chip floating\". In order to understand the underlying physics of the floating phenomena and predict process variables to eliminate the process defects, a process model has been. developed. The critical process variables include chip placement speed, chip placement force, dwell time, deposited underfill mass and underfill material properties such as viscosity, density, surface tension, wetting speed on the board, etc. A test chip and board was made such that chip floating over the board can be detected by testing the electric continuity of the path connecting the chip and board via the solder bumps. The effects of the critical process variables on the chip floating are investigated by a series of experiments and the results are compared to the theoretical model prediction for the model validation.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129078143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Minimization of splice loss between a single mode fiber and an erbium doped fiber 单模光纤与掺铒光纤之间剪接损耗的最小化

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008343

S. Pradhan, A. Mazloom, J. Arbulich, K. Srihari

引用次数: 5

Reel-to-reel manufacturability of flexible electrical interconnects and radio-frequency identification structures 柔性电气互连和射频识别结构的卷对卷可制造性

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008172

D. Lochun, E. Zeira, R. Menize

引用次数: 1

Modeling methodology for predicting the thermo-mechanical reliability of electronic packaging 预测电子封装热机械可靠性的建模方法

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008271

M. Thurston, G. Raiser, D. Chiang, S. Tandon, M. Mello

引用次数: 0

A web-based graduate course on design-for-reliability of electronic systems 电子系统可靠性设计的网络研究生课程

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008306

P. Mccluskey

引用次数: 4