52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)最新文献_第10页

Development of wafer thinning and double-sided bumping technologies for the three-dimensional stacked LSI 三维堆叠型大规模集成电路的晶圆薄化和双面凸化技术的发展

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008100

M. Sunohara, Tomonori Fujii, M. Hoshino, H. Yonemura, M. Tomisaka, Kenji Takahashi

引用次数: 16

3.125 Gbps /spl times/ 8 channels parallel interconnection module with low height MT receptacle connector for single mode fibers 3.125 Gbps /spl倍/ 8通道并行互连模块，具有用于单模光纤的低高度MT插座连接器

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008110

M. Iwase, T. Shirai, Y. Ishikawa, T. Nomura, A. Izawa, H. Mori, N. Shimoji, M. Shiino, R. Yuguchi

引用次数: 1

High quality RF passive integration using 35 /spl mu/m thick oxide manufacturing technology 采用35 /spl mu/m厚氧化物制造技术的高品质射频无源集成

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008224

I. Jeong, Choong-Mo Nam, Chang Yup Lee, Jung-Hoon Moon, Jongsoo Lee, Dong-Wook Kim, Y. Kwon

{"title":"High quality RF passive integration using 35 /spl mu/m thick oxide manufacturing technology","authors":"I. Jeong, Choong-Mo Nam, Chang Yup Lee, Jung-Hoon Moon, Jongsoo Lee, Dong-Wook Kim, Y. Kwon","doi":"10.1109/ECTC.2002.1008224","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008224","url":null,"abstract":"The strong pressure of cost and size reduction in wireless industry makes the phone makers find new and revolutionary solutions for their products. Among the various approaches, the passive integration is the most attractive way. To achieve both goals of dramatic size reduction and additional cost reduction, we developed low cost manufacturing technology for RF substrate and high performance process technology for RF integrated passive devices by electrochemically forming thick oxide on Si wafer and using Cu metal and BCB material for metal interconnection and interlayer. The fabricated substrate is conventional 6\" Si wafer with SiO/sub 2/ thickness of 25 /spl mu/m on the surface. This substrate showed the very good insertion loss of 0.03 dB/mm at 4 GHz, including conductive metal loss, in case of 50 /spl Omega/ coplanar transmission line (W=50 /spl mu/m, G=20 /spl mu/m), and provided cost-effective solution in RF passive integration. Based on these process technologies, we fabricated ultra high Q inductor on Si, which showed the maximum quality factor of 120. Several RFIPD (Integrated Passive Device) were also fabricated on thick oxide silicon and they showed good RF performances in spite of small chip size. In case of power divider, the insertion loss is below 0.5 dB and isolation is more than 25 dB. The 900 MHz low pass filter has 0.5 dB insertion loss and more than 25 dB attenuation at second and third harmonics. These will be widely utilized in hand-held module and system where the size or volumetric efficiency is a critical buying criterion.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130413624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

Effects of voids on bump chip carrier (BCC++) solder joint reliability 空隙对凸片载体(bcc++)焊点可靠性的影响

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008222

J. Lau, S. Erasmus, S. Pan

引用次数: 24

Thermal study of GaN-based HFET devices 氮化镓基HFET器件的热研究

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008159

Jeong H. Park, Selah Choe Park, M. Shin, C.C. Lee

引用次数: 2

Optimizing assembly factors to minimize interlayer die stress in a PBGA package 优化装配因素，最大限度降低 PBGA 封装中的层间模具应力

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008254

J. Weidler, R. Newman, C. Zhai

{"title":"Optimizing assembly factors to minimize interlayer die stress in a PBGA package","authors":"J. Weidler, R. Newman, C. Zhai","doi":"10.1109/ECTC.2002.1008254","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008254","url":null,"abstract":"As die have increased in complexity and density, there has been an associated growth in the number of die layers. To maximize field reliability interlayer die stress over use conditions should be minimized, which will minimize the occurrence of die layer delamination and associated die cracking failures. Interlayer die stress is affected by various packaging and assembly parameters, such as die thickness, die attach epoxy fillet geometry, molding compound, and saw cut process. Twenty-four lots of plastic ball-grid array (PBGA) packages were assembled in a 35/spl times/35 mm PBGA-352, as separate legs of a design of experiments (DOE). The die thickness was varied between 6 and 14 mils, in increments of 2 mils. The die were attached with three different fillet height geometries; standard fillet height (50% all around with no mismatch), hi/low fillet height (90% on one side of the die and 25% fillet height on the side opposite), and hi/even fillet height (90% all around with no mismatch). Each lot was subjected to reliability testing to determine which combination of assembly parameters yielded the most robust PBGA package. A PBGA package assembled with a 12 mil thick die and standard fillet produced the most robust product. The data indicates that the molding compound type and saw cut process did not affect the robustness of the package over the range of molding compounds and saw cut processes studied. The data also indicates that the thickness of the die is the parameter that most directly affects die cracking. In addition, the geometry of the fillet height also contributes to mechanical stress on the die, though the magnitude of its contribution is not as great. Two-dimensional mechanical modeling supports the experimental results. Furthermore, mechanical modeling provides a qualitative analysis of the stress induced on the die from the fillet geometry as well as the relationship between die thickness and package induced die stress.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125778799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Influence of grinding process on semiconductor chip strength 磨削工艺对半导体芯片强度的影响

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008323

Enboa Wu, I.G. Shih, Y.N. Chen, S.C. Chen, C.Z. Tsai, C. Shao

{"title":"Influence of grinding process on semiconductor chip strength","authors":"Enboa Wu, I.G. Shih, Y.N. Chen, S.C. Chen, C.Z. Tsai, C. Shao","doi":"10.1109/ECTC.2002.1008323","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008323","url":null,"abstract":"Studies the strength distribution of semiconductor chips on a wafer, and the influence of the back-side grinding process on the chip strength.. The three-point bending test, complying with the ASTM standard E855, was adopted to measure the chip strength. The first set of test vehicles is from three 8-inch wafers. One is of 28 mils thick without backside grinding, and the other two are backside ground to 18 mils and 11 mils thick. Then, four 6-inch wafers were used as the second set of test vehicles. The first two were 22 mils thick which were backside ground and the other two wafers were 27 mils in thickness without grinding. The third set of test vehicles was formed by three 8-inch wafers of identical thickness (11-mil) and size, but they were backside ground by different factories. It is found that, whereas the chip strength distributed randomly on a wafer which did not experience any backside grinding, any wafers that were subjected to backside grinding always resulted in weak regions. The averaged strength for the chips in the weak region was approximately 30% lower than the averaged strength calculated from the whole wafer, regardless of the chip dimension.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129705339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Connector interconnections to transmission lines for 40 Gb/s broadband applications 连接器连接到传输线，用于40gb /s宽带应用

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008227

A. M. Lyons, A. Becker, Young-Min Lee, C. Metz, S.-E. Shih, P. Auernhammer, S. Weisser

{"title":"Connector interconnections to transmission lines for 40 Gb/s broadband applications","authors":"A. M. Lyons, A. Becker, Young-Min Lee, C. Metz, S.-E. Shih, P. Auernhammer, S. Weisser","doi":"10.1109/ECTC.2002.1008227","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008227","url":null,"abstract":"The electrical performance of Sub-Miniature Coaxial Connector (SMCC) interconnections to transmission lines was investigated in a frequency range up to 50 GHz. A family of test coupons was built to evaluate the following design parameters of SMCC connector interfaces: transmission line structures, solder pad shapes and structures, SMCC connector structures and grounding of the SMCC housing. Electromagnetic 3D full-wave solver (HFSS) was used not only to elucidate the main design factors affecting the electrical performance of the interconnection but also to compare between model results and measured S-parameters. Low-loss SMCC interconnections to well designed Grounded Co-Planar Waveguide (GCPW) and microstrip transmission lines were achieved without significant resonances up to a frequency range of 50 GHz. Grounding between the SMCC connector housing and bottom ground plane of the transmission line was found to be the most critical factor for electrical loss. Transmission line design and connector structure details were also found to have a significant impact on performance.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129948958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Mechanical effects of copper through-vias in a 3D die-stacked module 铜通孔在三维模堆模块中的力学效应

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008138

N. Tanaka, T. Sato, Y. Yamaji, T. Morifuji, M. Umemoto, K. Takahashi

引用次数: 42

Online-offline laser ultrasonic quality inspection tool for multi-layer chip capacitors 多层片式电容器在线-离线激光超声质量检测工具

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008098

D. Erdahl, I. C. Ume

{"title":"Online-offline laser ultrasonic quality inspection tool for multi-layer chip capacitors","authors":"D. Erdahl, I. C. Ume","doi":"10.1109/ECTC.2002.1008098","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008098","url":null,"abstract":"The advent of surface mounted devices has allowed continued size decreases in electronic packages. However, the decrease in device size has led to other manufacturing problems. Therefore, as devices decrease in size, inspection technology must be developed to maintain consistent levels of quality without increasing manufacturing process time. The focus of most inspection technology is on finding defects with solder joint interconnects, but some devices, such as multi- layer chip capacitors (MLCCs), have failures not relating to the solder connection. Defects in MLCCs, known as flex cracks, are commonly caused by manufacturing processes, and no current means of detection exists, unless the cracks cause a device to fail a functional test. A laser ultrasonic and interferometric system, providing a non-contact, nondestructive and online approach for microelectronic package quality inspection, is designed and presented. A pulsed infrared laser excites a specimen into vibration through laser-generated ultrasound, and the vibration displacement is measured using an interferometer. Differentiation between acceptable and unacceptable devices is achieved using signal-processing techniques that compare waveforms between two devices. Results are presented or a case study involving MLCCs that have intentionally induced flex cracks, causing the devices to fail. The system has the capability of detecting open connections and flex cracks in the MLCC packages.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130863019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11