No-flow underfill process modeling and analysis for low cost, high throughput flip chip assembly

Abstract

No-flow underfill process has been widely accepted as a key technology to implement low-cost, high-throughput flip chip on board (FCOB) assembly because of the elimination of processing steps such as flux application, flux residue cleaning, capillary underfill flow and secondary thermal curing of the underfill. While feasibility tests for the low-cost, high-throughput flip chip assembly based on no-flow underfill over a wide range of flip chip configurations are underway, unfamiliar process defects that have not been observed in the conventional capillary flow process are newly emerging. Of those new process defects, "chip floating" over the board surface after chip placement process is a critical issue that may significantly impact process yield when process variables are not properly controlled. It was found that much of the yield losses observed post reflow is attributed to the "chip floating". In order to understand the underlying physics of the floating phenomena and predict process variables to eliminate the process defects, a process model has been. developed. The critical process variables include chip placement speed, chip placement force, dwell time, deposited underfill mass and underfill material properties such as viscosity, density, surface tension, wetting speed on the board, etc. A test chip and board was made such that chip floating over the board can be detected by testing the electric continuity of the path connecting the chip and board via the solder bumps. The effects of the critical process variables on the chip floating are investigated by a series of experiments and the results are compared to the theoretical model prediction for the model validation.