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2006 International Conference on Microelectronics最新文献

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A Portable Clock Recovery Circuit (CRC) For Systems-On-Chip Serial Data Communication 用于片上系统串行数据通信的便携式时钟恢复电路(CRC)
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373301
M. Elrabaa
{"title":"A Portable Clock Recovery Circuit (CRC) For Systems-On-Chip Serial Data Communication","authors":"M. Elrabaa","doi":"10.1109/ICM.2006.373301","DOIUrl":"https://doi.org/10.1109/ICM.2006.373301","url":null,"abstract":"An all-digital clock recovery circuit that is capable of extracting the clock embedded in the serial data stream is presented. The new CRC can retime the output clock with the received data within two bit transitions. The absence of analog filters or other analog blocks gives it a much smaller area than conventional circuitry. Also, being fully-digital, it can be described, simulated and synthesized using hardware description languages and be ported to any technology (thus supporting system on a chip designs). Circuit operation and performance was demonstrated using a 0.13 mum, 1.2 V CMOS technology and T-Spicereg simulations.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129090549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Crystal-Tolerant Fully Integrated Frequency Synthesizer For GPS Receivers: System Perspective 用于GPS接收机的晶体容限全集成频率合成器:系统视角
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373280
T. Elesseily, K. Sharaf
{"title":"A Crystal-Tolerant Fully Integrated Frequency Synthesizer For GPS Receivers: System Perspective","authors":"T. Elesseily, K. Sharaf","doi":"10.1109/ICM.2006.373280","DOIUrl":"https://doi.org/10.1109/ICM.2006.373280","url":null,"abstract":"This paper presents the system level design of a frequency synthesizer for dual band GPS receivers that can be easily integrated in wireless phones (mainly GSM mobile phones). For the ease of integration with GSM wireless systems the synthesizer can tolerate most of the common GSM crystals, besides the GPS crystals. The presented synthesizer was designed to target a low IF down conversion receiver with a tolerable IF range of 10% around 4.092 MHz which allows the use of the famous 10/13/26 MHz GSM crystals and all the GPS crystals. The designed frequency synthesizer generates the LO signals for both L1/L2 bands (1.5713 GHz/1.2317 GHz) with an average phase noise of -95 dBc/Hz,consuming 4.0 5mW/4.5 mW for L1/L2 respectively at 1.2V supply.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"389 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131418750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
CMOS Digitally Programmable Inductance CMOS数字可编程电感
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373286
H. Alzaher, N. Tasadduq
{"title":"CMOS Digitally Programmable Inductance","authors":"H. Alzaher, N. Tasadduq","doi":"10.1109/ICM.2006.373286","DOIUrl":"https://doi.org/10.1109/ICM.2006.373286","url":null,"abstract":"A CMOS digitally programmable active lossless inductor realization is proposed. The proposed inductor is based on current and voltage followers and uses R-2R ladder to provide digital tuning of the inductance value. The followers support the use of the simulated inductor for applications in few MHz range. Whereas the use of R-2R provide an additional advantage of realizing high inductance value suitable for very low frequency applications. The proposed inductor is used in synthesizing cascadable biquadratic filters. Simulation results are presented.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125441867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Design of FIR Filters Using Identical Subfilters of Even Length 用均匀长度的同子滤波器设计FIR滤波器
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373272
S. Zanjani, S. M. Fakhraie, O. Shoaei, M. Salehi
{"title":"Design of FIR Filters Using Identical Subfilters of Even Length","authors":"S. Zanjani, S. M. Fakhraie, O. Shoaei, M. Salehi","doi":"10.1109/ICM.2006.373272","DOIUrl":"https://doi.org/10.1109/ICM.2006.373272","url":null,"abstract":"This article presents an analytic development for the design of linear-phase FIR digital filters with reduced computational and hardware complexity. The proposed approach is based on a frequency transformation implemented by replacing a subfilter in a prototype filter. The previous approach forced subfilters and prototype filters to be of odd length, while this approach supports subfilters and prototype filters of even length. Depending on the specifications of the filter, either the previous method or our proposed method can give the optimal solution for the design of the required filter. It has been shown by means of an example that the overall composite FIR filter with the proposed approach contributes to a saving of 22%, 22% and 22% in the number of adders, delays and multipliers respectively compared to the previous approach.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124555642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Fixed Delay Infinite-Bit Split Adder Architecture and Its Application in Real-Time Image Processing 一种固定延迟无限位分割加法器结构及其在实时图像处理中的应用
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373300
A. F. Hajjar
{"title":"A Fixed Delay Infinite-Bit Split Adder Architecture and Its Application in Real-Time Image Processing","authors":"A. F. Hajjar","doi":"10.1109/ICM.2006.373300","DOIUrl":"https://doi.org/10.1109/ICM.2006.373300","url":null,"abstract":"A fixed delay split adder is presented. The adder breaks the total addition into sum and reminder with an expected reminder percentage of about 0.33% of the total sum. The adder is capable of producing the outputs in 6 gate delays regardless of the inputs bit-size. The proposed adder is applied to two realtime image processing applications and results showed very close matching to the perfect cases when ignoring the reminder.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125077529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Reconfigurable Low Power FIR Filter based on Partitioned Multipliers 基于分割乘法器的可重构低功耗FIR滤波器
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373273
Farhat Abbas Shah, H. Jamal, Muhammad Akhtar Khan
{"title":"Reconfigurable Low Power FIR Filter based on Partitioned Multipliers","authors":"Farhat Abbas Shah, H. Jamal, Muhammad Akhtar Khan","doi":"10.1109/ICM.2006.373273","DOIUrl":"https://doi.org/10.1109/ICM.2006.373273","url":null,"abstract":"This paper presents a low power programmable FIR filter based on partitioned multipliers. Architecture chosen for implementation is conventional direct form. Power efficient techniques like unsigned multiplication and reduction of switching activity are used. Paper presents power, area and speed analysis of the proposed design. FIR Filter is fully parameterized, dynamically programmable and technology independent. Results are presented for 20-tap FIR filter implemented on Xilinx Vertex-II FPGA 2s200fg256-6. Maximum power saving of 48.2% is achieved with an area overhead of 2.08 % only.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116411934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A 4×4 Tin Oxide Gas Sensor Array with On-chip Signal Pre-processing 具有片上信号预处理的4×4氧化锡气体传感器阵列
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373641
B. Guo, A. Bermak, P. Chan, G. Yan
{"title":"A 4×4 Tin Oxide Gas Sensor Array with On-chip Signal Pre-processing","authors":"B. Guo, A. Bermak, P. Chan, G. Yan","doi":"10.1109/ICM.2006.373641","DOIUrl":"https://doi.org/10.1109/ICM.2006.373641","url":null,"abstract":"This paper presents a monolithic 4times4 tin oxide gas sensor array together with on-chip multiplexing and differential read-out circuitry. In contrast to the conventional voltage divider read-out technique, a novel differential read-out circuit (DRC) for tin oxide gas sensors is proposed. The output of the DRC is simply proportional to the difference between the voltage on the two electrodes of the sensor but not to the transistor parameters such as mobility and threshold voltage, neither to the supply voltage. A robust fabrication process focusing on the integration of the CMOS circuitry and the MEMS structures is described. The monolithic sensor array and its processing circuitry have been implemented in our in-house 5 mum process. Experimental results showed good linearity at the output of the DRC for a wide range of sensor resistance variation (over 20 MOmega). Results also show good thermal characteristic leading to only 15.5 mW power consumption for 300 degC operating temperature.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134311408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of a Low-Power High-Rate Ultra-Wideband Modulator for 5.8-10.6 GHz 5.8 ~ 10.6 GHz低功耗高速率超宽带调制器设计
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373278
M. Salehi, A. Nabavi, N. Ghadimi
{"title":"Design of a Low-Power High-Rate Ultra-Wideband Modulator for 5.8-10.6 GHz","authors":"M. Salehi, A. Nabavi, N. Ghadimi","doi":"10.1109/ICM.2006.373278","DOIUrl":"https://doi.org/10.1109/ICM.2006.373278","url":null,"abstract":"A pulse modulator for ultra-wideband (UWB) transmitters is designed and simulated using 0.13-mum CMOS technology. 8-GHz carrier frequency is modulated into pulses with Gaussian envelope and 1-ns time-width to push the spectrum to 5.8-10.6-GHz band, and to satisfy FCC mask. By using 2-ns pulse-width, it is also possible to utilize the modulator at two sub-bands of 6-8 GHz and 8-10 GHz. The transmitter is low power since it employs a digital structure, and also supports high data rates due to using I/Q modulation. The architecture of modulator consists of Johnson counter, multiplier, current adder, and RF mixer. The key element in the design is ETSPC flip flops that fulfill high-speed and low-power requirements in precision timing. The power-speed trade-off is optimized by decreasing the size of the FFs, and using direct conversion structure for RF mixer. The power consumption of the modulator from 1.2-V power supply is as low as 4.5 mW for the rate of 2 Gchip/s at 8-GHz center frequency.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122542386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Finding low activity op-code sets using genetic computing 利用遗传计算寻找低活度操作码集
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373265
M. Dastjerdi-Mottaghi, M. Riazati, M. Daneshtalab, Z. Navabi
{"title":"Finding low activity op-code sets using genetic computing","authors":"M. Dastjerdi-Mottaghi, M. Riazati, M. Daneshtalab, Z. Navabi","doi":"10.1109/ICM.2006.373265","DOIUrl":"https://doi.org/10.1109/ICM.2006.373265","url":null,"abstract":"In this paper, we propose a genetic algorithm for finding the optimum op-code sequence for instruction set of a given processor. The sequence, which we look for, raises the least possible average signal transitions on the address bus of the given processor. The algorithm takes the probability of each instruction pair. Then randomly generates some op-code sequence as the initial population. Afterwards it iteratively uses some problem specific heuristics to generate a better population based upon the existing population and the table of pair probabilities, in this manner better and better populations are generated until (after about 200000 iterations) no better op-code sequence can be generated at which time the algorithm stops. Results, for MIPS-R4000, show that the proposed algorithm reduces the average switching activity of the address bus by 44%.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122547183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Exponentially Tapering Ground Wires for Elmore Delay Reduction in On Chip Interconnects 在片上互连中降低Elmore延迟的指数锥形地线
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373276
M. A. Karami, A. Afzali-Kusha
{"title":"Exponentially Tapering Ground Wires for Elmore Delay Reduction in On Chip Interconnects","authors":"M. A. Karami, A. Afzali-Kusha","doi":"10.1109/ICM.2006.373276","DOIUrl":"https://doi.org/10.1109/ICM.2006.373276","url":null,"abstract":"In this paper inter metal capacitors of ground wires are considered, for the first time in Elmore delay calculations of clock distribution interconnect networks. Analytical models for capacitance calculation of inter metal wires which are exponentially tapered are presented. In addition, the tapering of the ground wire for reducing this delay is proposed. The results show that by a exponentially tapering of the ground wires in the clock distribution networks , a 17% reduction in the Elmore delay of interconnects is achieved in compare with not tapering ground wires.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122706971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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