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2006 International Conference on Microelectronics最新文献

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A Digital Clock Re-Timing Circuit for On-Chip Source-Synchronous Serial Links 用于片上源同步串行链路的数字时钟重定时电路
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373303
M. Elrabaa
{"title":"A Digital Clock Re-Timing Circuit for On-Chip Source-Synchronous Serial Links","authors":"M. Elrabaa","doi":"10.1109/ICM.2006.373303","DOIUrl":"https://doi.org/10.1109/ICM.2006.373303","url":null,"abstract":"A new all-digital circuit scheme for clock and data re-timing functions for on-chip high-speed source synchronous data communications, such as in burst-mode data transmission over a network-on-chip is introduced. The new technique is non-PLL-based and is capable of retiming the output clock with the received data within one data transition. Being fully digital makes its area much smaller than conventional circuitry. It can also be described by any hardware description language, simulated, and synthesized into any digital process. This enables it to be ported from one technology to another and support system on a chip (SOC) designs. The design concept is demonstrated with T-Spicereg simulations using a 0.13 mum digital CMOS technology.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115709255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
General Two-Party Oblivious Circuit Evaluation 一般两方无关电路评估
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373304
S. T. Faraj
{"title":"General Two-Party Oblivious Circuit Evaluation","authors":"S. T. Faraj","doi":"10.1109/ICM.2006.373304","DOIUrl":"https://doi.org/10.1109/ICM.2006.373304","url":null,"abstract":"A two-party oblivious circuit evaluation (2P- OCE) protocol is a way for a party Alice owns a secret x and another party Bob owns a secret y to compute the value of an agreed upon function f(x,y), where f can be computed by a polynomial sized Boolean circuit. This is done in such a way that Alice learns nothing about y and Bob learns nothing about x, except for what can be inferred from one's private input and the public value of f(x,y). This paper presents a general, correct, fair, honest, and maximum privacy 2P-OCE protocol that is based on a set of reductions to more simple cryptographic primitives. The protocol uses the primitives of one-out-of-two oblivious transfer (1-2-OT) and bit commitment (BC) as black boxes. Consequently, the protocol may be implemented with or without computational assumptions, depending on the type of 1-2-OT and BC used by participants.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"10 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123856976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Checkpointing Technique for Rollback Error Recovery in Embedded Systems 嵌入式系统回滚错误恢复的检查点技术
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373295
M. Bashiri, S. Miremadi, M. Fazeli
{"title":"A Checkpointing Technique for Rollback Error Recovery in Embedded Systems","authors":"M. Bashiri, S. Miremadi, M. Fazeli","doi":"10.1109/ICM.2006.373295","DOIUrl":"https://doi.org/10.1109/ICM.2006.373295","url":null,"abstract":"In this paper, a general checkpointing technique for rollback error recovery for embedded systems is proposed and evaluated. This technique is independent of used processor and employs the most important feature in control flow error detection mechanisms to simplify checkpoint selection and to minimize the overall code overhead. In this way, during the implementation of a control flow checking mechanism, the checkpoints are added to the program. To evaluate the checkpointing technique, a pre-processor is implemented that selects and adds the checkpoints to three workload programs running in an 8051 microcontroller-based system. The evaluation is based on 3000 experiments for each checkpoint.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"85 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113992398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Soft-Core Processors for Embedded Systems 嵌入式系统的软核处理器
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373294
J. G. Tong, Ian D. L. Anderson, Mohammed A. S. Khalid
{"title":"Soft-Core Processors for Embedded Systems","authors":"J. G. Tong, Ian D. L. Anderson, Mohammed A. S. Khalid","doi":"10.1109/ICM.2006.373294","DOIUrl":"https://doi.org/10.1109/ICM.2006.373294","url":null,"abstract":"A soft-core processor is a hardware description language (HDL) model of a specific processor (CPU) that can be customized for a given application and synthesized for an ASIC or FPGA target. In many applications, soft-core processors provide several advantages over custom designed processors such as reduced cost, flexibility, platform independence and greater immunity to obsolescence. Embedded systems are hardware and software components working together to perform a specific function. Usually they contain embedded processors that are often in the form of soft-core processors that execute software code. This paper presents a survey of soft-core processors that are used in embedded systems. Several soft-core processors available from commercial vendors and open-source communities are reviewed and compared based on major architectural features. In addition, several real world examples of embedded systems that employ soft-core processors are summarized. As the complexity of embedded systems continues to increase, it is expected that the usage of customizable soft-core processors will become more widespread.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134079644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 137
Adaptive Neural Network Model for SOI-MOSFET I-V Characteristic Including Self-Heating Effect 含自热效应的SOI-MOSFET I-V特性自适应神经网络模型
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373640
M. A. Karami, A. Afzali-Kusha
{"title":"Adaptive Neural Network Model for SOI-MOSFET I-V Characteristic Including Self-Heating Effect","authors":"M. A. Karami, A. Afzali-Kusha","doi":"10.1109/ICM.2006.373640","DOIUrl":"https://doi.org/10.1109/ICM.2006.373640","url":null,"abstract":"In this paper, a model for SOI MOSFETs which considers the self-heating effect is proposed. The model which is based on a multi layer perceptron (MLP) neural network, generates the drain current as a function of the gate-source voltage, drain-source voltage, and the device temperature. Based on the current, the temperature of the device channel is calculated. The neural network adapts itself with the channel temperature which can be calculated by an equivalent thermal model for the SOI device.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114551500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
MEMS AD/DA Converters MEMS AD/DA转换器
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373285
A. Majid
{"title":"MEMS AD/DA Converters","authors":"A. Majid","doi":"10.1109/ICM.2006.373285","DOIUrl":"https://doi.org/10.1109/ICM.2006.373285","url":null,"abstract":"MEMS analog-to-digital and digital-to-analog converters are proposed using parallel plate electrostatic actuators under bias. Deformable plates supported by springs are used with bias applied voltage which determines the amount of static displacement needed for equilibrium condition. In analog-to-digital arrangement, eight different spring displacements are tapped off the spring corresponding to eight binary decoded voltages. At spring tapped connections, MOS switches are switched on connecting a digital high voltage level at these locations so that when a certain analog voltage is applied on the moving plate of the capacitor, the spring is displaced to one of these locations, enabling different binary voltages to all switches up to that level. The digital binary voltages are fed to an 8-3 priority encoder to obtain the digital value. In digital-to-analog arrangement, the input binary voltage is decoded to different spring locations which correspond to resistances making up a potentiometer circuit for the output analog voltage.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116354897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Low Power Base-Band Circuit for Low-IF Wireless PAN Receivers 一种低中频无线PAN接收机的低功率基带电路
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373279
R. Zanbaghi, M. Atarodi, M. Moezzi, A. Tajalli
{"title":"A Low Power Base-Band Circuit for Low-IF Wireless PAN Receivers","authors":"R. Zanbaghi, M. Atarodi, M. Moezzi, A. Tajalli","doi":"10.1109/ICM.2006.373279","DOIUrl":"https://doi.org/10.1109/ICM.2006.373279","url":null,"abstract":"A fully integrated CMOS base-band part of a low-IF WPAN receiver is presented, which consists of an active complex filter, an automatic gain control unit, and a 10-Bit Pipe-Line ADC. The highlights of the receiver include a low- power active complex filter with a nonconventional Gm-C structure and a high-resolution, low power pipe line ADC using averaging and double sampling techniques. The chip was designed on a small die using 0.18-um standard CMOS process. The filter provides more than 55 db image rejection ratio and IM3 of -50 dB for 1.9 & 2.1 MHz signals with 0.2Vpp. The converter has a peak SFDR of 61 dB, maximum DNL of 0.5 LSB, and INL of 0.9 LSB. The all parts of the scheme consume an active current about 4mA from a 1.8-V power supply.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"26 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124832128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A High Compliance Input and Output Regulated Body-Driven Current Mirror for Deep-Submicron CMOS 用于深亚微米CMOS的高顺应性输入输出调节体驱动电流镜
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373642
M.W. Murphy, E. El-Masry, A. Elshurafa
{"title":"A High Compliance Input and Output Regulated Body-Driven Current Mirror for Deep-Submicron CMOS","authors":"M.W. Murphy, E. El-Masry, A. Elshurafa","doi":"10.1109/ICM.2006.373642","DOIUrl":"https://doi.org/10.1109/ICM.2006.373642","url":null,"abstract":"A current mirror circuit that uses body-driven MOSFETs to achieve an ultra-low input and output voltage is presented. High-gain amplifiers, suitable for a deep submicron process, are used to provide matching as well as input and output regulation. Simulation results were verified with measurements performed on a fabricated chip using the 90-nm CMOS process from ST-Microelectronics.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"236 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128333803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Hot Block Ring Counter: A Low Power Synchronous Ring Counter 热块环计数器:一个低功率同步环计数器
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373266
M. Dastjerdi-Mottaghi, A. Naghilou, M. Daneshtalab, A. Afzali-Kusha, Z. Navabi
{"title":"Hot Block Ring Counter: A Low Power Synchronous Ring Counter","authors":"M. Dastjerdi-Mottaghi, A. Naghilou, M. Daneshtalab, A. Afzali-Kusha, Z. Navabi","doi":"10.1109/ICM.2006.373266","DOIUrl":"https://doi.org/10.1109/ICM.2006.373266","url":null,"abstract":"In this paper, we propose a new and low-power architecture for synchronous ring counters which can noticeably reduce the switching activity of the conventional ring counters. To achieve the goal we partition the ring counter into some blocks for each of which we use a special clock gator. The Hot block (the block in which the '1' exists) is the only block the flip-flops of which are clocked. The delay and area overhead of the proposed clock gator is independent of the block size; this enables designer to freely resize the blocks and compromise with area and power overheads. The latency increase in the proposed architecture is independent of the counter width and depends only on the technology. For 90 nm technology it increases the latency by 5%. The architecture noticeably (about 85%) reduces the total switching activity of the counter especially for wide counters.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129666145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Efficient Algorithm for Positive-polarity Reed-muller Expansions of reversible circuits 可逆电路正极Reed-muller展开的有效算法
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373267
Jing Hu, Guangsheng Ma, Gang Feng
{"title":"Efficient Algorithm for Positive-polarity Reed-muller Expansions of reversible circuits","authors":"Jing Hu, Guangsheng Ma, Gang Feng","doi":"10.1109/ICM.2006.373267","DOIUrl":"https://doi.org/10.1109/ICM.2006.373267","url":null,"abstract":"In this paper, we build mathematical modeling for reversible circuits and derive required parameters of cost function from this modeling. The heuristic algorithm plots out reversible circuit into some partitions, uses a priority queue based on search tree and explores candidate components at each partition in order of utilization ratio. We demonstrate that using this heuristic, path delay can be reduced by 8% compared to existing synthesis method. The improvements increase for strict delay constraints making synthesis especially important for high performance and a large number of inputs and outputs designs.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122384212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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