{"title":"A Low Power Base-Band Circuit for Low-IF Wireless PAN Receivers","authors":"R. Zanbaghi, M. Atarodi, M. Moezzi, A. Tajalli","doi":"10.1109/ICM.2006.373279","DOIUrl":null,"url":null,"abstract":"A fully integrated CMOS base-band part of a low-IF WPAN receiver is presented, which consists of an active complex filter, an automatic gain control unit, and a 10-Bit Pipe-Line ADC. The highlights of the receiver include a low- power active complex filter with a nonconventional Gm-C structure and a high-resolution, low power pipe line ADC using averaging and double sampling techniques. The chip was designed on a small die using 0.18-um standard CMOS process. The filter provides more than 55 db image rejection ratio and IM3 of -50 dB for 1.9 & 2.1 MHz signals with 0.2Vpp. The converter has a peak SFDR of 61 dB, maximum DNL of 0.5 LSB, and INL of 0.9 LSB. The all parts of the scheme consume an active current about 4mA from a 1.8-V power supply.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"26 7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 International Conference on Microelectronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICM.2006.373279","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A fully integrated CMOS base-band part of a low-IF WPAN receiver is presented, which consists of an active complex filter, an automatic gain control unit, and a 10-Bit Pipe-Line ADC. The highlights of the receiver include a low- power active complex filter with a nonconventional Gm-C structure and a high-resolution, low power pipe line ADC using averaging and double sampling techniques. The chip was designed on a small die using 0.18-um standard CMOS process. The filter provides more than 55 db image rejection ratio and IM3 of -50 dB for 1.9 & 2.1 MHz signals with 0.2Vpp. The converter has a peak SFDR of 61 dB, maximum DNL of 0.5 LSB, and INL of 0.9 LSB. The all parts of the scheme consume an active current about 4mA from a 1.8-V power supply.