发布求助
文献互助 智能选刊 最新文献

2006 International Conference on Microelectronics最新文献

筛选
英文 中文
Low Power Area Efficient High Data Rate 16-bit ABS Crypto Processor 低功耗区域高效高数据速率16位ABS加密处理器
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373298
H. Jamal, S. Farhan, S. A. Khan
{"title":"Low Power Area Efficient High Data Rate 16-bit ABS Crypto Processor","authors":"H. Jamal, S. Farhan, S. A. Khan","doi":"10.1109/ICM.2006.373298","DOIUrl":"https://doi.org/10.1109/ICM.2006.373298","url":null,"abstract":"This paper presents a 16-bit AES architecture for low power and high bit rate applications. The novelty is in breaking the original 32-bit boundary based AES algorithm into a scalable architecture to work with 8-bit and 16-bit data set. 8-bit architecture is already developed. This new work offers a choice to the designer to use 8-bit or 16-bit algorithm for area and power efficient FPGA implementation. The novelty of the new development is still around the mix-column design. The complex matrix multiplication component and standard transformations of the 32-bit AES algorithm are transformed now to support 16-bit operations as well, simultaneously qualifying for applications requiring high data rates. The design has been further embellished by a memory based microprogrammed controller, which simplifies the control process of the algorithm and makes the FPGA platform viable for effective hardware utilization. The proposed architecture technique reuses same hardware resources for both key expansion and encryption.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130340375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Scalability Evaluation of a Hybrid Routing Architecture for Multi-FPGA Systems 多fpga系统混合路由架构的可扩展性评估
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373292
Mohammed A. S. Khalid, Viktor Salitrennik
{"title":"Scalability Evaluation of a Hybrid Routing Architecture for Multi-FPGA Systems","authors":"Mohammed A. S. Khalid, Viktor Salitrennik","doi":"10.1109/ICM.2006.373292","DOIUrl":"https://doi.org/10.1109/ICM.2006.373292","url":null,"abstract":"Multi-FPGA systems (MFSs) are used as custom computing machines, logic emulators, and rapid prototyping vehicles. A key aspect of these systems is their programmable routing architecture which is the manner in which wires, FPGAs, and Field-Programmable Interconnect Devices (FPIDs) are connected. Several routing architectures for MFSs have been proposed and previous research has shown that the partial crossbar is one of the best existing architectures. A new routing architecture, called the Hybrid Complete-Graph and Partial- Crossbar (HCGP), was proposed by Khalid and was shown to provide superior speed and cost compared to partial crossbar. In this paper we address the issue of scalability of the HCGP routing architecture. The motivation for this work was to evaluate the suitability of the HCGP architecture for a future rapid prototyping system product that was being developed at Cadence. Experimental results show that the HCGP architecture is scalable and can be used with the state-of-the-art, high gate count FPGAs.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122982630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Accelerated Multi-Grid Scheme for Substrate Coupling Modeling and Analysis 衬底耦合建模与分析的加速多网格方案
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373269
M. A. Karami, N. Masoumi, E. Afjei
{"title":"Accelerated Multi-Grid Scheme for Substrate Coupling Modeling and Analysis","authors":"M. A. Karami, N. Masoumi, E. Afjei","doi":"10.1109/ICM.2006.373269","DOIUrl":"https://doi.org/10.1109/ICM.2006.373269","url":null,"abstract":"This paper proposes a novel method for substrate coupling modeling and analysis. This method is based on accelerated multi-grid, finite difference simulation. In this method the final value of impedance in each stage of modeling is calculated by considering the results of both two previous stage grids. This calculation performed with different weighting factors for two previous stages. This method, with best weighting factors result in 75% decrease in simulation time for low frequency substrate modeling compare with simple multi-grid method. The time saving will improve with increasing the accuracy and number of points for simulation.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113968829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Very Fast and Low Power Pseudo-Incrementer for Address Bus Encoder/Decoder 一种用于地址总线编码器/解码器的快速低功耗伪增量器
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373274
Hadi Parandeh-Afshar, A. Afzali-Kusha, Ali Khakifirouz
{"title":"A Very Fast and Low Power Pseudo-Incrementer for Address Bus Encoder/Decoder","authors":"Hadi Parandeh-Afshar, A. Afzali-Kusha, Ali Khakifirouz","doi":"10.1109/ICM.2006.373274","DOIUrl":"https://doi.org/10.1109/ICM.2006.373274","url":null,"abstract":"This paper presents a very fast yet low power pseudo incrementer structure which may be used in address bus encoders/decoders. This structure, which is based on the ripple carry incrementer, is much faster than the incrementer. Using this structure, the delay and the power of address bus encoders/decoders may be reduced considerably. Analytical and synthesis results show that the structure is faster than current incrementer circuits while its circuit area and power are much smaller than those of current fast incrementers.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131499176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Slice-Based Automatic Hardware/Software Partitioning Heuristic 一种基于切片的自动硬件/软件分区启发式方法
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373289
H. Parandeh-Afshar, A. Tootoonchian, M. Yousefpour, O. Fatemi, M. Hashemi
{"title":"A Slice-Based Automatic Hardware/Software Partitioning Heuristic","authors":"H. Parandeh-Afshar, A. Tootoonchian, M. Yousefpour, O. Fatemi, M. Hashemi","doi":"10.1109/ICM.2006.373289","DOIUrl":"https://doi.org/10.1109/ICM.2006.373289","url":null,"abstract":"In this paper, a novel level-based hardware/software partitioning heuristic has been proposed. The algorithm operates on functional blocks of designs represented as directed acyclic graphs (DAG), with the objective of minimizing the processing time under various hardware area constraints. In most existing methods, the communication overhead and the fact that the vertices mapped onto the same computing unit have less communication, is overlooked during the partitioning decision, while the proposed algorithm considers this fact during partitioning.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128915170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Custom Instruction Integration Method within Reconfigurable SoC and FPGA Devices 可重构SoC和FPGA器件中的自定义指令集成方法
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373284
Y. Aoudni, G. Gogniat, M. Abid, J. Philippe
{"title":"Custom Instruction Integration Method within Reconfigurable SoC and FPGA Devices","authors":"Y. Aoudni, G. Gogniat, M. Abid, J. Philippe","doi":"10.1109/ICM.2006.373284","DOIUrl":"https://doi.org/10.1109/ICM.2006.373284","url":null,"abstract":"General-purpose processors that are utilized as cores are often incapable of achieving the challenging cost, performance, and power demands of high-performance audio, video, and networking applications. To meet these demands, most systems employ a number of hardware accelerators to off-load the computationally demanding portions of the application. As an alternative to this strategy, we examine customizing the computation capabilities of a core processor for a particular application. Our goal is to generate a prototype of reconfigurable custom instruction SoC to answer application request using FPGA technology. To give more flexibility to system, we addressed customized core with coarse and finite granularity. In this paper, we provide an overview of a method to identify coarse and finite grain instruction set extensions in application code and integration process in reconfigurable SoC based on NIOSII processor core. 3D synthesis application was proposed as a case study for experimentation.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126464129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Synthesis of MVL Functions - Part I: The Genetic Algorithm Approach MVL函数的综合-第一部分:遗传算法方法
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373290
Bambang A. B. Sarif, M. Abd-El-Barr
{"title":"Synthesis of MVL Functions - Part I: The Genetic Algorithm Approach","authors":"Bambang A. B. Sarif, M. Abd-El-Barr","doi":"10.1109/ICM.2006.373290","DOIUrl":"https://doi.org/10.1109/ICM.2006.373290","url":null,"abstract":"Multiple-valued logic (MVL) has been used in the design of a number of logic systems, including memory, multi-level data communication coding, and a number of special purpose digital processors. Several algorithms have been proposed in the literature for synthesis of multiple valued logic functions. None of these algorithms provides absolute optimum results for synthesis of these functions. The search space is too large to be explored by deterministic algorithms. In this paper, a Genetic Algorithm based algorithm for synthesis of MVL functions is proposed. The algorithm is tested using 200 randomly generated 2-variable 4-valued functions. The results obtained show that the introduced algorithm outperforms the deterministic technique based on the direct cover approach in terms of the average number of product terms required to realize a given MVL function.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121438712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Frequency Independent Phase Shifter 频率无关移相器
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373308
M. Al-Absi
{"title":"Frequency Independent Phase Shifter","authors":"M. Al-Absi","doi":"10.1109/ICM.2006.373308","DOIUrl":"https://doi.org/10.1109/ICM.2006.373308","url":null,"abstract":"A new simple and low cost frequency independent phase shifter is presented. The design is based on the simple op-amp phase shifter with programmable floating resistor and programmable capacitor. The phase shift can be varied using the programmable resistor. Compensation for the variation in the frequency is achieved using the programmable capacitor. Simulation results are also presented.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130449110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An Optimal Structure for Implementation of Digital Filters 数字滤波器的最优实现结构
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1587/elex.4.679
Shahabuddin Rahmanian, S. M. Fakhraie
{"title":"An Optimal Structure for Implementation of Digital Filters","authors":"Shahabuddin Rahmanian, S. M. Fakhraie","doi":"10.1587/elex.4.679","DOIUrl":"https://doi.org/10.1587/elex.4.679","url":null,"abstract":"In this paper, different structures for an elliptic filter with fixed point arithmetic are implemented and compared. The filter must be quantized for hardware implementation. This quantization is done in two steps. First the coefficients of filter are quantized and then the accuracy of internal nodes are limited. According to the simulation results, lattice and DF2- parallel structures have minimal sensitivity to coefficient quantization. Also, the area (gate count) that each of the structures occupy on the chip are computed. We show that overall, the DFl-parallel structure is the optimal structure for hardware implementation that requires minimal chip area at a reasonable precision.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116633962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An Ultra-Wideband Low-Noise Amplifier for 3-5-GHz Wireless Systems 一种用于3-5 ghz无线系统的超宽带低噪声放大器
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373644
A. Saghafi, A. Nabavi
{"title":"An Ultra-Wideband Low-Noise Amplifier for 3-5-GHz Wireless Systems","authors":"A. Saghafi, A. Nabavi","doi":"10.1109/ICM.2006.373644","DOIUrl":"https://doi.org/10.1109/ICM.2006.373644","url":null,"abstract":"In this paper, an ultra-wideband low-noise amplifier is designed and simulated in a 0.13-mum CMOS technology for a 3-5-GHz UWB system. For ultra-wideband operation, shunt-series feedback topology is used. To improve noise performance, the amplifier employs inductive load. Biasing point variation which occurs due to the resistive feedback is fixed by adding a capacitor in series with feedback. Thus, the desirable gain is achieved with a lower power consumption. Simulations show a -3-dB gain bandwidth of 6 GHz between 2 GHz and 8 GHz, a minimum noise figure of 1.9 dB in the 3-5-GHz band, a power gain of 11.5 dB while consuming 13.9 mW.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133069659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信