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2006 International Conference on Microelectronics最新文献

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First Order Current Mode Filters and Multiphase Sinusoidal Oscillators Using MOCCIIs 基于moccii的一阶电流模式滤波器和多相正弦振荡器
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373288
I. A. Khan, P. Beg, M. T. Ahmed
{"title":"First Order Current Mode Filters and Multiphase Sinusoidal Oscillators Using MOCCIIs","authors":"I. A. Khan, P. Beg, M. T. Ahmed","doi":"10.1109/ICM.2006.373288","DOIUrl":"https://doi.org/10.1109/ICM.2006.373288","url":null,"abstract":"An insensitive current mode versatile first order filter section with single input and multiple outputs is realized. The realization uses two multi outputs current conveyors, only one grounded resistor and one grounded capacitor. The realized current mode section provides low-pass, high-pass and all-pass responses at different outputs without any component matching constraint. The all-pass section is then cascaded with the current mode non-inverting integrator to realize a current mode multiphase sinusoidal oscillator. Thus the realized current mode oscillator provides eight phase sinusoidal outputs with equal magnitudes. The current mode outputs are loaded with same valued resistive load to achieve the eight phase voltage mode sinusoidal outputs with equal magnitudes. All the realization were designed and simulated using PSPICE. The simulation results thus obtained, verify the theory.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121292686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 56
Design Feasibility Study For A 500 Gbits/s AES Cypher Decypher Engine 一种500gbits /s AES密码解密引擎设计可行性研究
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373299
A. Bouhraoua
{"title":"Design Feasibility Study For A 500 Gbits/s AES Cypher Decypher Engine","authors":"A. Bouhraoua","doi":"10.1109/ICM.2006.373299","DOIUrl":"https://doi.org/10.1109/ICM.2006.373299","url":null,"abstract":"A feasibility study for implementing the AES encryption algorithm in hardware achieving 500 Gbits/s is presented. The methodology followed in the process of obtaining the solution allowed us to reach a highly regular solution that is scalable.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115605268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A Simple Model for the Kink Effect for the Intrinsic p-channel Polysilicon thin film transistors 本征p沟道多晶硅薄膜晶体管扭结效应的简单模型
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373643
Mohammad. Jawaid Siddiqui, Samir Maqbool Al-Shariff, Abdur-Rahman F. AlMarshood
{"title":"A Simple Model for the Kink Effect for the Intrinsic p-channel Polysilicon thin film transistors","authors":"Mohammad. Jawaid Siddiqui, Samir Maqbool Al-Shariff, Abdur-Rahman F. AlMarshood","doi":"10.1109/ICM.2006.373643","DOIUrl":"https://doi.org/10.1109/ICM.2006.373643","url":null,"abstract":"In order to improve the modeling of polysilicon thin film transistors (Poly-Si-TFTs) a precise evaluation of the excess current due to impact ionization is needed. In this paper, we have proposed a simple model for the excess current resulting from the impact ionization occurring at high drain biases. Model is based on the estimation of the electric field in the saturated part of the channel. The electric field in the saturated region is obtained by the solution of the two-dimensional Poisson's equation. The model is semi-analytical and uses only one fitting parameter which is desirable for circuit simulation. The simulation results with the developed impact ionization current model are in excellent agreement with the available experimental output characteristics of the intrinsic p-channel Poly-Si-TFTs.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"2022 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128073927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effect of Glitches on the Efficiency of Components Region-Constrained Placement as a Fast Approach to Reduce FPGAs Dynamic Power Consumption 小故障对元件区域约束布局效率的影响——一种快速降低fpga动态功耗的方法
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373307
S. Esmaeili, N. Khachab, M. Ghannam
{"title":"Effect of Glitches on the Efficiency of Components Region-Constrained Placement as a Fast Approach to Reduce FPGAs Dynamic Power Consumption","authors":"S. Esmaeili, N. Khachab, M. Ghannam","doi":"10.1109/ICM.2006.373307","DOIUrl":"https://doi.org/10.1109/ICM.2006.373307","url":null,"abstract":"The increased flexibility offered by FPGAs implies that more transistors are needed which leads to higher power consumption per logic gate. FPGAs power consumption is fast becoming an essential design consideration especially for mobile systems with a limited power supply. The effect of components' region-constrained placement on reducing internal nets total capacitance and the corresponding change in internal nets' total dynamic power consumption is investigated. Two logic circuits were specified as components covering around 80% of total FPGA busy gates. These components are multiplexers and adders along with multipliers. Each of these components was implemented on two of Xilinx FPGA 's families, namely; Spartan II and Virtex. Gate- level power estimation for different region-constrained placements of each logic circuit was carried out using the Xilinx hierarchal power distribution analyzer, XPower.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124183204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Efficient Network-on-Chip Architecture Based on the Fat-Tree (FT) Topology 基于胖树(FT)拓扑的高效片上网络架构
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373259
A. Bouhraoua, M.E. Elrabaa
{"title":"An Efficient Network-on-Chip Architecture Based on the Fat-Tree (FT) Topology","authors":"A. Bouhraoua, M.E. Elrabaa","doi":"10.1109/ICM.2006.373259","DOIUrl":"https://doi.org/10.1109/ICM.2006.373259","url":null,"abstract":"A novel approach for an efficient network-on-chip using a modified Fat Tree is presented. Contention is eliminated and latency is reduced through an improved topology and router architecture. The adopted topology increases performance without a substantial increase in the routing cost. This is achieved by using an improved buffer-less, paremeterizable router architecture. The proposed router architecture is simple to implement yet can achieve the required packet collision avoidance. Simulation results that show the level of performance achieved by both the topology and the router architecture are presented. A throughput of more than 90% is achieved way above the 40-50% usually seen in other networks on chips.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"385 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121773378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Low-latency Multi-Level Mesh Topology for NoCs 面向noc的低延迟多级网状拓扑
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373261
M. Saneei, A. Afzali-Kusha, Z. Navabi
{"title":"Low-latency Multi-Level Mesh Topology for NoCs","authors":"M. Saneei, A. Afzali-Kusha, Z. Navabi","doi":"10.1109/ICM.2006.373261","DOIUrl":"https://doi.org/10.1109/ICM.2006.373261","url":null,"abstract":"In this paper, we introduce a new topology for network on chips which is named multi-level mesh topology. The multi-level mesh topology is basically similar to the 2D-mesh with this difference that we have several meshes that have some common routers. This architecture reduces the latency and the dynamic power consumption in NoCs and can improve the communication throughput in high traffic applications. This architecture reduces the latency of 3 x 3, 5 x 5, and 7 x 7 2-level mesh architectures about 12.5%, 21.4%, and 18.5% related to mesh architecture, respectively. The results are expected to improve further if a better adaptive routing algorithm is utilized.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121342432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Finding Agent-Based Energy-Efficient Routing in Sensor Networks using Parallel Genetic Algorithm 利用并行遗传算法寻找基于agent的传感器网络节能路由
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373281
E. Rahmani, S. M. Fakhraie, M. Kamarei
{"title":"Finding Agent-Based Energy-Efficient Routing in Sensor Networks using Parallel Genetic Algorithm","authors":"E. Rahmani, S. M. Fakhraie, M. Kamarei","doi":"10.1109/ICM.2006.373281","DOIUrl":"https://doi.org/10.1109/ICM.2006.373281","url":null,"abstract":"Recent advances in wireless sensor networks have led us to search for new routing protocols specifically those designed for sensor networks where energy awareness is an essential consideration. In this paper, a modified cost-energy (MCE) combined scheme for energy efficient routing in sensor networks has been proposed. We have added a parameter to CE combined scheme and obtained better results. We have used parallel genetic algorithm (PGA) to determine the parameters of MCE combined scheme. By using the proposed scheme, due to lower power consumption, the life time of the sensor network is prolonged. Simulation results show about 40% improvement in \"average energy consumption per agent\" of the network comparing MCE combined scheme with other schemes discussed in this paper.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130019884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A New Polyphase Current-Mode Filter Using Digitally-Programmable CCCII 一种基于数字可编程CCCII的多相电流模式滤波器
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373287
S. M. Al-Shahrani, M. Al-Gahtani
{"title":"A New Polyphase Current-Mode Filter Using Digitally-Programmable CCCII","authors":"S. M. Al-Shahrani, M. Al-Gahtani","doi":"10.1109/ICM.2006.373287","DOIUrl":"https://doi.org/10.1109/ICM.2006.373287","url":null,"abstract":"A novel polyphase current-mode filter suitable for CMOS integrated circuit implementation is presented. The circuit uses two digitally-programmable current-controlled current-conveyors, MOSFETs, and two grounded capacitors. The proposed circuit can be operated from a low power supply voltage (plusmn1.5 V) and its parameters enjoy low active- and passive-sensitivity. Simulation results using CMOS CCCII are included.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116298837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Modified Leakage-Biased Domino Circuit with Low-Power and Low-Delay Characteristics 具有低功耗低延迟特性的改进漏偏多米诺电路
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373282
E. Rahmani, Z. Pajouhi, N. Kazemian-Amiri, A. Afzali-Kusha
{"title":"Modified Leakage-Biased Domino Circuit with Low-Power and Low-Delay Characteristics","authors":"E. Rahmani, Z. Pajouhi, N. Kazemian-Amiri, A. Afzali-Kusha","doi":"10.1109/ICM.2006.373282","DOIUrl":"https://doi.org/10.1109/ICM.2006.373282","url":null,"abstract":"In this paper, a new domino logic structure whose architecture is based on a leakage biased (LB) domino circuit is introduced. The proposed technique improves the performance and the dynamic power consumption of the circuits. In addition, the number of transistors is reduced leading to a lower silicon area. Simulations are done for various circuits. Compared to the LB method, in a full adder circuit, the delay is reduced more than 25%; also, the dynamic and the static powers have reduced slightly.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"52 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133948860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Improved Assertion Lifetime via Assertion-Based Testing Methodology 通过基于断言的测试方法改进断言生命周期
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373264
M. Riazati, S. Mohammadi, A. Afzali-Kusha, Z. Navabi
{"title":"Improved Assertion Lifetime via Assertion-Based Testing Methodology","authors":"M. Riazati, S. Mohammadi, A. Afzali-Kusha, Z. Navabi","doi":"10.1109/ICM.2006.373264","DOIUrl":"https://doi.org/10.1109/ICM.2006.373264","url":null,"abstract":"Assertions-based verification (ABV) has been widely used in digital design validation. Assertions are HDL-syntaxed representation of design specification and used as a functional error detection mechanism. During the process of designing with HDLs, assertions are imported which could fire in case of violation during testbench run. Although these assertions are mostly used during simulation and for verifying the functional correctness of the design, but as they illustrate the specifications of a design, it is likely that their lifetime could be extended by embedding them in the chip to detect low level faults like stuck-at faults. In this paper, we introduce a new automatable assertion-based on-line testing methodology. Experimental results show that the synthesis of assertions into a chip, and then using them for online testing, can provide an acceptable coverage for stuck-at faults.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123868043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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