Low-latency Multi-Level Mesh Topology for NoCs

Abstract

In this paper, we introduce a new topology for network on chips which is named multi-level mesh topology. The multi-level mesh topology is basically similar to the 2D-mesh with this difference that we have several meshes that have some common routers. This architecture reduces the latency and the dynamic power consumption in NoCs and can improve the communication throughput in high traffic applications. This architecture reduces the latency of 3 x 3, 5 x 5, and 7 x 7 2-level mesh architectures about 12.5%, 21.4%, and 18.5% related to mesh architecture, respectively. The results are expected to improve further if a better adaptive routing algorithm is utilized.