Custom Instruction Integration Method within Reconfigurable SoC and FPGA Devices

Abstract

General-purpose processors that are utilized as cores are often incapable of achieving the challenging cost, performance, and power demands of high-performance audio, video, and networking applications. To meet these demands, most systems employ a number of hardware accelerators to off-load the computationally demanding portions of the application. As an alternative to this strategy, we examine customizing the computation capabilities of a core processor for a particular application. Our goal is to generate a prototype of reconfigurable custom instruction SoC to answer application request using FPGA technology. To give more flexibility to system, we addressed customized core with coarse and finite granularity. In this paper, we provide an overview of a method to identify coarse and finite grain instruction set extensions in application code and integration process in reconfigurable SoC based on NIOSII processor core. 3D synthesis application was proposed as a case study for experimentation.