一种低中频无线PAN接收机的低功率基带电路

R. Zanbaghi, M. Atarodi, M. Moezzi, A. Tajalli
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引用次数: 2

摘要

提出了一种低中频WPAN接收机的全集成CMOS基带部分,它由一个有源复杂滤波器、一个自动增益控制单元和一个10位管道线ADC组成。该接收机的亮点包括采用非常规Gm-C结构的低功率有源复杂滤波器和采用平均和双采样技术的高分辨率低功率管道ADC。该芯片采用0.18微米标准CMOS工艺设计在一个小芯片上。该滤波器为0.2Vpp的1.9和2.1 MHz信号提供超过55 db的图像抑制比和-50 db的IM3。该转换器的峰值SFDR为61 dB,最大DNL为0.5 LSB, INL为0.9 LSB。该方案的所有部分都消耗来自1.8 v电源的约4mA的有源电流。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Low Power Base-Band Circuit for Low-IF Wireless PAN Receivers
A fully integrated CMOS base-band part of a low-IF WPAN receiver is presented, which consists of an active complex filter, an automatic gain control unit, and a 10-Bit Pipe-Line ADC. The highlights of the receiver include a low- power active complex filter with a nonconventional Gm-C structure and a high-resolution, low power pipe line ADC using averaging and double sampling techniques. The chip was designed on a small die using 0.18-um standard CMOS process. The filter provides more than 55 db image rejection ratio and IM3 of -50 dB for 1.9 & 2.1 MHz signals with 0.2Vpp. The converter has a peak SFDR of 61 dB, maximum DNL of 0.5 LSB, and INL of 0.9 LSB. The all parts of the scheme consume an active current about 4mA from a 1.8-V power supply.
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