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2006 International Conference on Microelectronics最新文献

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Prediction of Spectral Regrowth of Quasi-Memoryless Fifth-order RF Amplifiers under Multitone Excitation 准无记忆五阶射频放大器在多音激励下的频谱再生预测
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373309
N. Boulejfen, A. Harguem, F. Ghannouchi
{"title":"Prediction of Spectral Regrowth of Quasi-Memoryless Fifth-order RF Amplifiers under Multitone Excitation","authors":"N. Boulejfen, A. Harguem, F. Ghannouchi","doi":"10.1109/ICM.2006.373309","DOIUrl":"https://doi.org/10.1109/ICM.2006.373309","url":null,"abstract":"New formulas for estimating the spectral regrowth at the output of RF Power Amplifiers (RFPAs) have been proposed. The formulas predict the average output power spectral density (PSD) of fifth-order quasi- memoryless RFPAs, excited with uncorrelated tones. The efficiency of the proposed approach is demonstrated by predicting the spectral regrowth in a commercial RFPA for different input power levels. The obtained results were compared to those of a harmonic balance simulation and have shown a good accuracy and time efficiency.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122313309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Introducing Energy and Area Estimation in HW/SW Design Flow Based on Transaction Level Modeling 基于事务级建模的硬件/软件设计流程中的能量和面积估算
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373297
M. O. Cheema, O. Hammami
{"title":"Introducing Energy and Area Estimation in HW/SW Design Flow Based on Transaction Level Modeling","authors":"M. O. Cheema, O. Hammami","doi":"10.1109/ICM.2006.373297","DOIUrl":"https://doi.org/10.1109/ICM.2006.373297","url":null,"abstract":"Transaction level modeling (TLM) facilitates the system designer in decision making at early phases of electronic product development. Executable specifications obtained from TLM models are used for the exploration of various architectural parameters and configurations possible for a system. However, traditional design flows based on TLM don't take into account the area and energy consumption of the system which are inevitably the most important constraints in modern embedded system designs. Traditionally, area and energy estimation is incorporated in system design at RTL (Register Transfer Level) which comes later in system design cycles and most of the crucial design decisions for the system has already been taken at that stage. In this paper, we propose a methodology to incorporate area and energy estimation in TLM based system modeling. This methodology allows a system designer take system level design decisions in very early stages of system design hence avoiding redesign efforts and performance bottlenecks in advanced stages of a project. Results obtained by applying our methodology on an image processing application show the robustness of our approach.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126525497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A Quantitative Study on Layer-2 Packet Processing on a General Purpose Processor 通用处理器第二层数据包处理的定量研究
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373306
M. Salehi, R. Rafati, F. Baharvand, S. M. Fakhraie
{"title":"A Quantitative Study on Layer-2 Packet Processing on a General Purpose Processor","authors":"M. Salehi, R. Rafati, F. Baharvand, S. M. Fakhraie","doi":"10.1109/ICM.2006.373306","DOIUrl":"https://doi.org/10.1109/ICM.2006.373306","url":null,"abstract":"In this paper, we present a quantitative study that investigates implementation of a layer-2 switching application on a general purpose processor (GPP). The objective is to better understand the main challenges and tradeoffs in using such processors for packet processing applications. The goal of this study is to identify the architectural guidelines for successful development of an application specific instruction processor (ASIP) for such applications. To asses the performance of switching of packets with various lengths, a LEON2 RISC processor has been chosen as a GPP. The obtained results are compared together based on detailed instruction level profiling of the mentioned application.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129444390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Translinear-C Function Generator Translinear-C函数生成器
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373271
S. Hasan, I. A. Khan
{"title":"Translinear-C Function Generator","authors":"S. Hasan, I. A. Khan","doi":"10.1109/ICM.2006.373271","DOIUrl":"https://doi.org/10.1109/ICM.2006.373271","url":null,"abstract":"A novel function generator is realized using a multi output current controlled current conveyors (MOCCCIIs) based current mode band-pass filter, which can simultaneously provide four phase sinusoidal quadrature current outputs, square and triangular voltage outputs. The circuit basically uses only four MOCCCIIs and four grounded capacitors. The function generator enjoys attractive features such as use of grounded capacitors, wide range electronic tunability, low sensitivity figures and load insensitive current outputs. Moreover due to the absence of external resistors the circuit is very much suitable for monolithic implementation. The proposed function generator is designed and verified with excellent results.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134440096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
On-Line Testing and Diagnosis of Microcontroller 单片机在线测试与诊断
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373296
K. Elshafey, A. Elhosiny
{"title":"On-Line Testing and Diagnosis of Microcontroller","authors":"K. Elshafey, A. Elhosiny","doi":"10.1109/ICM.2006.373296","DOIUrl":"https://doi.org/10.1109/ICM.2006.373296","url":null,"abstract":"This paper presents an on-line testing and diagnosis approach of microcontroller. The proposed approach has been achieved through both fault masking and fault diagnosis algorithms. Concurrent testing technique through using triple modular redundancy (TMR) is required to mask the operational faults and specially tolerate the transient faults. For permanent faults and in parallel with TMR, an on-line and non-concurrent fault detection and diagnostic technique is used to locate the faulty elements. The fault detection and diagnostic technique uses a set of assembly programs that test the entire microcontroller instruction-sets called macros. The macros are able to excite all of the microcontroller functions. A macro is associated to each machine-level instruction; and composed of a few instructions, aimed at activating the target instruction with some operand values representing the macro parameters and propagates the results of its execution to an observable memory positions. A Simulation study has been done using Xilinx Foundation tool, VHDL, and an FPGA Vertix chip.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122617165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 3 to 5 GHz UWB SiGe HBT Low Noise Amplifier 一个3至5 GHz超宽带sigehbt低噪声放大器
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.3923/ITJ.2007.579.583
F. Touati, M. Loulou, M. Bouzid
{"title":"A 3 to 5 GHz UWB SiGe HBT Low Noise Amplifier","authors":"F. Touati, M. Loulou, M. Bouzid","doi":"10.3923/ITJ.2007.579.583","DOIUrl":"https://doi.org/10.3923/ITJ.2007.579.583","url":null,"abstract":"Ultra-wideband low-noise amplifiers (UWB LNA) operating in the low-frequency band (3.1-5 GHz) of UWB spectrum are presented. The designs consist of a cascode amplifier with wideband input matching techniques based on LC-ladder filters or shunt-feedback both combined with inductive peaking. Implemented with a SiGe HBT process, the LNAs give 18.0 dB gain, better than -20 dB input matching, and a return loss less than -34 dB, while consuming 11 mW under 1.5 V supply. The feedback LNA gives a better flat noise figure of 2.5 dB and an input IP3 of -6 dB at 5 GHz.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127015302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Double-edge Triggered Level Converter Flip-Flop with Feedback 带反馈的双边触发电平变换器触发器
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373263
A. Seyedi, A. Afzali-Kusha
{"title":"Double-edge Triggered Level Converter Flip-Flop with Feedback","authors":"A. Seyedi, A. Afzali-Kusha","doi":"10.1109/ICM.2006.373263","DOIUrl":"https://doi.org/10.1109/ICM.2006.373263","url":null,"abstract":"In this paper, a double-edge triggered level converter flip-flop (DE-LCFFF) is proposed. The flip-flop makes use of the conditional discharging technique which effectively suppress the dynamic power consumption during transition time and the self-precharging technique to automatically precharge its dynamic node after enough time. An explicit double-edge pulse generator is used to further decrease the power consumption in the proposed LCFF. In addition, the use of pass gate transistors and more simplified structure in the main block of DELCFFF leads to a less leakage power consumption. The increase in the speed is achieved by reducing the number of the stack transistors in the discharge path and using less complicated circuit structure. When compared to the previous level converter flip-flops, the proposed LCFF shows considerable reductions in the power consumption, the delay, and the area.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129429151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A MEMS Disk Resonator-Based Oscillator 一种基于MEMS磁盘谐振器的振荡器
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373270
M.M. El Khouly, Y. Nada, E. Hegazi, H. Ragai, M. Ghannam
{"title":"A MEMS Disk Resonator-Based Oscillator","authors":"M.M. El Khouly, Y. Nada, E. Hegazi, H. Ragai, M. Ghannam","doi":"10.1109/ICM.2006.373270","DOIUrl":"https://doi.org/10.1109/ICM.2006.373270","url":null,"abstract":"A fully integrated MEMS based oscillator using a MEMS disk resonator is presented. Parameter extraction for a circuit model of the disk resonator using ANSYS is carried out at 60.6 MHz. A PIERCE oscillator using the disk resonator is designed. The circuit simulations are presented. The different specs of the oscillator like frequency, phase noise and frequency stability are investigated. The effect of the presence of the disk resonator on the performance of the oscillator is demonstrated.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129923059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Interconnect-Efficient LDPC Code Design 高效互连LDPC代码设计
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373283
A. El-Maleh, B. Arkasosy, A.-A.M. Adrian
{"title":"Interconnect-Efficient LDPC Code Design","authors":"A. El-Maleh, B. Arkasosy, A.-A.M. Adrian","doi":"10.1109/ICM.2006.373283","DOIUrl":"https://doi.org/10.1109/ICM.2006.373283","url":null,"abstract":"In this paper, we present a new, hardware-oriented technique for designing Low Density Parity Check (LDPC) codes. The technique targets to achieve an interconnect- efficient architecture that reduces the area and delay of the decoder implementation while maintaining good error correction performance. With a fully parallel implementation of the LDPC decoder, the proposed design assumes a constraint on the interconnect wire length which has a direct impact on the maximum signal delay and power dissipation. Furthermore, this design approach is shown to lower interconnect routing congestion, and hence reduce the chip area and maximize chip utilization.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"74 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130491691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Synthesis of MVL Functions - Part II: The Ant Colony Optimization Approach MVL函数的合成-第二部分:蚁群优化方法
2006 International Conference on Microelectronics Pub Date : 2006-12-01 DOI: 10.1109/ICM.2006.373291
M. Abd El Barr, Bambang A. B. Sarif
{"title":"Synthesis of MVL Functions - Part II: The Ant Colony Optimization Approach","authors":"M. Abd El Barr, Bambang A. B. Sarif","doi":"10.1109/ICM.2006.373291","DOIUrl":"https://doi.org/10.1109/ICM.2006.373291","url":null,"abstract":"In this paper, an ant colony optimization (ACO) based algorithm for synthesis of Multiple-Valued Logic (MVL) functions is proposed. The algorithm is tested using 50000 randomly generated 2-variable 4-valued functions. The proposed approach was compared to the existing direct cover techniques. The results obtained show that the proposed algorithm outperforms other approaches in terms of the average number of product terms required to realize a given MVL function.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134214559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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