A Fixed Delay Infinite-Bit Split Adder Architecture and Its Application in Real-Time Image Processing

Abstract

A fixed delay split adder is presented. The adder breaks the total addition into sum and reminder with an expected reminder percentage of about 0.33% of the total sum. The adder is capable of producing the outputs in 6 gate delays regardless of the inputs bit-size. The proposed adder is applied to two realtime image processing applications and results showed very close matching to the perfect cases when ignoring the reminder.