{"title":"一种固定延迟无限位分割加法器结构及其在实时图像处理中的应用","authors":"A. F. Hajjar","doi":"10.1109/ICM.2006.373300","DOIUrl":null,"url":null,"abstract":"A fixed delay split adder is presented. The adder breaks the total addition into sum and reminder with an expected reminder percentage of about 0.33% of the total sum. The adder is capable of producing the outputs in 6 gate delays regardless of the inputs bit-size. The proposed adder is applied to two realtime image processing applications and results showed very close matching to the perfect cases when ignoring the reminder.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Fixed Delay Infinite-Bit Split Adder Architecture and Its Application in Real-Time Image Processing\",\"authors\":\"A. F. Hajjar\",\"doi\":\"10.1109/ICM.2006.373300\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A fixed delay split adder is presented. The adder breaks the total addition into sum and reminder with an expected reminder percentage of about 0.33% of the total sum. The adder is capable of producing the outputs in 6 gate delays regardless of the inputs bit-size. The proposed adder is applied to two realtime image processing applications and results showed very close matching to the perfect cases when ignoring the reminder.\",\"PeriodicalId\":284717,\"journal\":{\"name\":\"2006 International Conference on Microelectronics\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 International Conference on Microelectronics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICM.2006.373300\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 International Conference on Microelectronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICM.2006.373300","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Fixed Delay Infinite-Bit Split Adder Architecture and Its Application in Real-Time Image Processing
A fixed delay split adder is presented. The adder breaks the total addition into sum and reminder with an expected reminder percentage of about 0.33% of the total sum. The adder is capable of producing the outputs in 6 gate delays regardless of the inputs bit-size. The proposed adder is applied to two realtime image processing applications and results showed very close matching to the perfect cases when ignoring the reminder.
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