M. Dastjerdi-Mottaghi, M. Riazati, M. Daneshtalab, Z. Navabi
{"title":"Finding low activity op-code sets using genetic computing","authors":"M. Dastjerdi-Mottaghi, M. Riazati, M. Daneshtalab, Z. Navabi","doi":"10.1109/ICM.2006.373265","DOIUrl":null,"url":null,"abstract":"In this paper, we propose a genetic algorithm for finding the optimum op-code sequence for instruction set of a given processor. The sequence, which we look for, raises the least possible average signal transitions on the address bus of the given processor. The algorithm takes the probability of each instruction pair. Then randomly generates some op-code sequence as the initial population. Afterwards it iteratively uses some problem specific heuristics to generate a better population based upon the existing population and the table of pair probabilities, in this manner better and better populations are generated until (after about 200000 iterations) no better op-code sequence can be generated at which time the algorithm stops. Results, for MIPS-R4000, show that the proposed algorithm reduces the average switching activity of the address bus by 44%.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 International Conference on Microelectronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICM.2006.373265","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper, we propose a genetic algorithm for finding the optimum op-code sequence for instruction set of a given processor. The sequence, which we look for, raises the least possible average signal transitions on the address bus of the given processor. The algorithm takes the probability of each instruction pair. Then randomly generates some op-code sequence as the initial population. Afterwards it iteratively uses some problem specific heuristics to generate a better population based upon the existing population and the table of pair probabilities, in this manner better and better populations are generated until (after about 200000 iterations) no better op-code sequence can be generated at which time the algorithm stops. Results, for MIPS-R4000, show that the proposed algorithm reduces the average switching activity of the address bus by 44%.