{"title":"基于分割乘法器的可重构低功耗FIR滤波器","authors":"Farhat Abbas Shah, H. Jamal, Muhammad Akhtar Khan","doi":"10.1109/ICM.2006.373273","DOIUrl":null,"url":null,"abstract":"This paper presents a low power programmable FIR filter based on partitioned multipliers. Architecture chosen for implementation is conventional direct form. Power efficient techniques like unsigned multiplication and reduction of switching activity are used. Paper presents power, area and speed analysis of the proposed design. FIR Filter is fully parameterized, dynamically programmable and technology independent. Results are presented for 20-tap FIR filter implemented on Xilinx Vertex-II FPGA 2s200fg256-6. Maximum power saving of 48.2% is achieved with an area overhead of 2.08 % only.","PeriodicalId":284717,"journal":{"name":"2006 International Conference on Microelectronics","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":"{\"title\":\"Reconfigurable Low Power FIR Filter based on Partitioned Multipliers\",\"authors\":\"Farhat Abbas Shah, H. Jamal, Muhammad Akhtar Khan\",\"doi\":\"10.1109/ICM.2006.373273\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a low power programmable FIR filter based on partitioned multipliers. Architecture chosen for implementation is conventional direct form. Power efficient techniques like unsigned multiplication and reduction of switching activity are used. Paper presents power, area and speed analysis of the proposed design. FIR Filter is fully parameterized, dynamically programmable and technology independent. Results are presented for 20-tap FIR filter implemented on Xilinx Vertex-II FPGA 2s200fg256-6. Maximum power saving of 48.2% is achieved with an area overhead of 2.08 % only.\",\"PeriodicalId\":284717,\"journal\":{\"name\":\"2006 International Conference on Microelectronics\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"19\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 International Conference on Microelectronics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICM.2006.373273\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 International Conference on Microelectronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICM.2006.373273","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Reconfigurable Low Power FIR Filter based on Partitioned Multipliers
This paper presents a low power programmable FIR filter based on partitioned multipliers. Architecture chosen for implementation is conventional direct form. Power efficient techniques like unsigned multiplication and reduction of switching activity are used. Paper presents power, area and speed analysis of the proposed design. FIR Filter is fully parameterized, dynamically programmable and technology independent. Results are presented for 20-tap FIR filter implemented on Xilinx Vertex-II FPGA 2s200fg256-6. Maximum power saving of 48.2% is achieved with an area overhead of 2.08 % only.
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