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2022 International Electron Devices Meeting (IEDM)最新文献

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Theoretical and Empirical Insight into Dopant, Mobility and Defect States in W Doped Amorphous In2 O3 for High-Performance Enhancement Mode BEOL Transistors 高性能增强模式BEOL晶体管中W掺杂非晶in2o3掺杂物、迁移率和缺陷态的理论和经验见解
2022 International Electron Devices Meeting (IEDM) Pub Date : 2022-12-03 DOI: 10.1109/IEDM45625.2022.10019366
Yaoqiao Hu, H. Ye, K. A. Aabrar, Sharadindu Gopal Kirtania, W. Chakraborty, S. Datta, Kyeongjae Cho
{"title":"Theoretical and Empirical Insight into Dopant, Mobility and Defect States in W Doped Amorphous In2 O3 for High-Performance Enhancement Mode BEOL Transistors","authors":"Yaoqiao Hu, H. Ye, K. A. Aabrar, Sharadindu Gopal Kirtania, W. Chakraborty, S. Datta, Kyeongjae Cho","doi":"10.1109/IEDM45625.2022.10019366","DOIUrl":"https://doi.org/10.1109/IEDM45625.2022.10019366","url":null,"abstract":"Tungsten (W) doped amorphous In<inf>2</inf> O<inf>3</inf> (IWO) enable BEOL-compatible enhancement mode (E-mode) nFETs with record performance such as I<inf>ON</inf> ~500μA/μm, I<inf>ON</inf>/I<inf>OFF</inf> ratio~10<sup>9</sup> and ideal SS ~60mV/dec. The critical role of tungsten (W) doping in amorphous In<inf>2</inf> O<inf>3</inf> (a-In<inf>2</inf> O<inf>3</inf>) for IWO FET is explored and revealed here for the first time using first-principles simulation and experimentation. We show that 1% W is the optimal doping for controlling carrier concentration and achieving the highest mobility for high-performance E-mode IWO FETs. Higher W-O bond dissociation energy suppresses oxygen vacancy (V<inf>O</inf>), leading to improved thermal and threshold voltage (V<inf>TH</inf>) stability. A defect gap states model is proposed and their influence on FET operation is investigated. This work provides guidance on mitigation of defects and further improvement in FET performance and V<inf>TH</inf> stability.","PeriodicalId":275494,"journal":{"name":"2022 International Electron Devices Meeting (IEDM)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114726340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Ferroelectric and Interlayer Co-optimization with In-depth Analysis for High Endurance FeFET 铁电和层间协同优化与高续航力场效应管的深入分析
2022 International Electron Devices Meeting (IEDM) Pub Date : 2022-12-03 DOI: 10.1109/IEDM45625.2022.10019465
Yuejia Zhou, Zhongxin Liang, Wenpu Luo, M. Yu, Runteng Zhu, X. Lv, Jiachen Li, Qianqian Huang, Fei Liu, Kechao Tang, Ru Huang
{"title":"Ferroelectric and Interlayer Co-optimization with In-depth Analysis for High Endurance FeFET","authors":"Yuejia Zhou, Zhongxin Liang, Wenpu Luo, M. Yu, Runteng Zhu, X. Lv, Jiachen Li, Qianqian Huang, Fei Liu, Kechao Tang, Ru Huang","doi":"10.1109/IEDM45625.2022.10019465","DOIUrl":"https://doi.org/10.1109/IEDM45625.2022.10019465","url":null,"abstract":"In face of the critical endurance issue, for the first time we take a holistic perspective to co-optimize the ferroelectric materials and interlayer in FeFET. Compared to the common HZO based gate stack, the novel combination of Hf0.95 Al0.05 O2+Al2 O3 enhances the endurance to $gt 5 times 10 ^{9}$ cycles while maintaining a retention > 10 years. In-depth analysis based on DFT and DQSCV reveal the reduction of interlayer electric field and interface charge trapping as the mechanism of optimization. We also develop a distributed interface trap model to correlate different trapping dynamics with the interlayer property in each device. This work pushes forward the understanding and development of high endurance strategy for FeFET.","PeriodicalId":275494,"journal":{"name":"2022 International Electron Devices Meeting (IEDM)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114808634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Highly reliable STT-MRAM adopting advanced MTJs with controlled domain wall pinning 高可靠的STT-MRAM采用先进的mtj与可控域壁钉
2022 International Electron Devices Meeting (IEDM) Pub Date : 2022-12-03 DOI: 10.1109/IEDM45625.2022.10019352
J. Park, J. H. Kim, J. M. Kim, J. Kim, D. Apalkov, A. Okada, H. Sato, J. Jeong, Y. Cho, U. Pi, Y. Kim, Y. S. Park, K. M. Song, K. Kim, D. Jeong, D. S. Kim, C. Kim, I. Kim, S. H. Han, K. Lee, J. Lee, Y. J. Song, G. Koh, B. Kuh, J. Lee, J. H. Song
{"title":"Highly reliable STT-MRAM adopting advanced MTJs with controlled domain wall pinning","authors":"J. Park, J. H. Kim, J. M. Kim, J. Kim, D. Apalkov, A. Okada, H. Sato, J. Jeong, Y. Cho, U. Pi, Y. Kim, Y. S. Park, K. M. Song, K. Kim, D. Jeong, D. S. Kim, C. Kim, I. Kim, S. H. Han, K. Lee, J. Lee, Y. J. Song, G. Koh, B. Kuh, J. Lee, J. H. Song","doi":"10.1109/IEDM45625.2022.10019352","DOIUrl":"https://doi.org/10.1109/IEDM45625.2022.10019352","url":null,"abstract":"We demonstrate highly reliable STT-MRAM whose array-level write error has been eliminated by lowering the density of domain wall pinning sites in the MTJs. The core part of investigation includes the identification and quantification of domain wall pinning sites, characterization and modeling of the pinning sites, and correlation of the density of pinning sites with array-level write error rate. The experimental results show that domain wall pinning is geometrically localized and reproduced upon the repeated writing cycles. By controlling the domain wall pinning, we obtain high-density MTJ array having superior reliability without notable trailing bits of write fail.","PeriodicalId":275494,"journal":{"name":"2022 International Electron Devices Meeting (IEDM)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131856017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A > 64 Multiple States and > 210 TOPS/W High Efficient Computing by Monolithic Si/CAAC-IGZO + Super-Lattice ZrO2/Al2 O3/ZrO2 for Ultra-Low Power Edge AI Application 单片Si/CAAC-IGZO +超晶格ZrO2/ al2o3 /ZrO2超低功耗边缘人工智能应用的A > 64多态和> 210 TOPS/W高效计算
2022 International Electron Devices Meeting (IEDM) Pub Date : 2022-12-03 DOI: 10.1109/IEDM45625.2022.10019324
M.-C. Chen, S. Ohshita, S. Amano, Y. Kurokawa, S. Watanabe, Y. Imoto, Y. Ando, Wen-Hsuang Hsieh, C.H. Chang, C. Wu, S. Chuang, H. Yoshida, M. Lu, M. Liao, S. Chang, S. Yamazaki
{"title":"A > 64 Multiple States and > 210 TOPS/W High Efficient Computing by Monolithic Si/CAAC-IGZO + Super-Lattice ZrO2/Al2 O3/ZrO2 for Ultra-Low Power Edge AI Application","authors":"M.-C. Chen, S. Ohshita, S. Amano, Y. Kurokawa, S. Watanabe, Y. Imoto, Y. Ando, Wen-Hsuang Hsieh, C.H. Chang, C. Wu, S. Chuang, H. Yoshida, M. Lu, M. Liao, S. Chang, S. Yamazaki","doi":"10.1109/IEDM45625.2022.10019324","DOIUrl":"https://doi.org/10.1109/IEDM45625.2022.10019324","url":null,"abstract":"We present a novel Si/CAACFIGZO + SuperLattice ZrO2/Al2 O3/ZrO2 (SL-ZAZ) analog in-memory computing (AiMC) chip by monolithic 3D technique with the high thermal stability of Si/OS process. The SL-ZAZ not just improves storage capacitance > 50 %, but also makes leakage current lower > 30% compared with our last year’s IEDM work. Due to this study, the monolithic Si/CAAC-IGZO + SL-ZAZ technique can further reduce unit cell layout area by 25 % for ultra-low power edge A I application. This monolithic AiMC chip achieves > 64 multiple weighting states, an operation energy efficiency > 210 TOPS/W, and an inference accuracy can keep over 90 % (MNIST) even at 125°C high temperature operation.","PeriodicalId":275494,"journal":{"name":"2022 International Electron Devices Meeting (IEDM)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131915597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
ITO Schottky Diode wth Record fT Beyond 400 GHz: Exploring Thickness Depdendant Film Property and Novel Heterogeneous Design 超过400 GHz记录fT的ITO肖特基二极管:探索厚度依赖的薄膜特性和新的异质设计
2022 International Electron Devices Meeting (IEDM) Pub Date : 2022-12-03 DOI: 10.1109/IEDM45625.2022.10019408
Kaizhen Han, Chengkuan Wang, Yuye Kang, Long Liu, Gong Zhang, Yue Chen, Xiao Gong
{"title":"ITO Schottky Diode wth Record fT Beyond 400 GHz: Exploring Thickness Depdendant Film Property and Novel Heterogeneous Design","authors":"Kaizhen Han, Chengkuan Wang, Yuye Kang, Long Liu, Gong Zhang, Yue Chen, Xiao Gong","doi":"10.1109/IEDM45625.2022.10019408","DOIUrl":"https://doi.org/10.1109/IEDM45625.2022.10019408","url":null,"abstract":"We report the discovery of a strong thickness dependent electrical property of ultra-thin indium-tin-oxide (ITO) film when ITO thickness (TITO) enters sub-10 nm regime: a transition from metal-like to SEMI-like. We further propose a heterogeneous structure design in Schottky diodes to make full use of such discovery so that thin SEMI-like ITO was used for Schottky barrier formation and thick metal-like ITO was used to minimize the contact resistance. Together with the optimization of the O2 flow during sputtering deposition, breakthrough device performance was realized, including a rectifying ratio of 5 orders and a cut-off frequency (fT) of 422 GHz in the device with the shortest diode length (LD) of 35 nm. The device also exhibits outstanding ION of 116.6 $mu$A/$mu$m, low ideality factor of 1.06, as well as a promising efficient energy harvesting capability with a current responsivity of 18 A/W.","PeriodicalId":275494,"journal":{"name":"2022 International Electron Devices Meeting (IEDM)","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133886398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Transient Thermal and Electrical Co-Optimization of BEOL Top-Gated ALD In₂O₃ FETs on Various Thermally Conductive Substrates Including Diamond 包括金刚石在内的各种导热衬底上BEOL顶门控ALD的瞬态热电协同优化
2022 International Electron Devices Meeting (IEDM) Pub Date : 2022-12-03 DOI: 10.1109/IEDM45625.2022.10019438
Pai-Ying Liao, S. Alajlouni, Zuxun Zhang, Z. Lin, M. Si, J. Noh, T. Feygelson, M. Tadjer, A. Shakouri, P. Ye
{"title":"Transient Thermal and Electrical Co-Optimization of BEOL Top-Gated ALD In₂O₃ FETs on Various Thermally Conductive Substrates Including Diamond","authors":"Pai-Ying Liao, S. Alajlouni, Zuxun Zhang, Z. Lin, M. Si, J. Noh, T. Feygelson, M. Tadjer, A. Shakouri, P. Ye","doi":"10.1109/IEDM45625.2022.10019438","DOIUrl":"https://doi.org/10.1109/IEDM45625.2022.10019438","url":null,"abstract":"In this work, we co-optimize the transient thermal and electrical characteristics of top-gated (TG), ultrathin, atomic-layer-deposited (ALD), back-end-of-line (BEOL) compatible indium oxide (In2 O3) transistors on various thermally conductive substrates by visualization of the self-heating effect (SHE) utilizing an ultrafast high-resolution (HR) thermo-reflectance (TR) imaging system and overcome the thermal challenges through substrate thermal management and short-pulse measurement. At the steady-state, the temperature increase $(Delta mathrm{T})$ of the devices on highly resistive silicon (HR Si) and diamond substrates are roughly 6 and 13 times lower than that on SiO $_{2} /$Si substrate, due to the higher thermal conductivities $(kappa) $ of HR Si and diamond. Consequently, ultrahigh drain current (ID) of 3.7 mA$/ mu mathrm{m}$ at drain voltage (VDS) of 1.4 V with direct current (DC) measurement is achieved with TG ALD In2 O3 FETs on diamond substrate. Furthermore, transient thermal study shows that it takes roughly 350 and 300 ns for the devices to heat-up and cool-down to the steady-states, being independent on the substrate. The extracted time constants of heat-up $(tau_{h})$ and cool-down $(tau_{c})$ processes are 137 and 109 ns, respectively. By employing electrical short-pulse measurement with pulse width (tpulse) shorter than $tau_{h}$, the SHE can be significantly reduced. Accordingly, a higher ID of 4.3 mA$/ mu mathrm{m}$ is realized with a 1.9nm-thick In2 O3 FET on HR Si substrate after co-optimization.","PeriodicalId":275494,"journal":{"name":"2022 International Electron Devices Meeting (IEDM)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132982433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Steep-Slope Negative Quantum Capacitance Field-Effect Transistor 陡坡负量子电容场效应晶体管
2022 International Electron Devices Meeting (IEDM) Pub Date : 2022-12-03 DOI: 10.1109/IEDM45625.2022.10019359
Yafen Yang, Kai Zhang, Yi Gu, Parameswari Raju, Qiliang Li, Li Ji, Lin Chen, D. Ioannou, Q. Sun, D. Zhang, Hao Zhu
{"title":"Steep-Slope Negative Quantum Capacitance Field-Effect Transistor","authors":"Yafen Yang, Kai Zhang, Yi Gu, Parameswari Raju, Qiliang Li, Li Ji, Lin Chen, D. Ioannou, Q. Sun, D. Zhang, Hao Zhu","doi":"10.1109/IEDM45625.2022.10019359","DOIUrl":"https://doi.org/10.1109/IEDM45625.2022.10019359","url":null,"abstract":"For the first time, we report the design and fabrication of a steep-slope negative quantum capacitance field-effect transistor (NQCFET) with a single-layer (SL)-graphene encapsulated in the gate stack of a MoS2 FET. Subthermionic steep switching is achieved with a minimum subthreshold slope (SS) of 31 mV/dec with negligible hysteresis. The contribution of negative quantum capacitance from the low density of states in the electron system in SL-graphene has been experimentally and theoretically explored.","PeriodicalId":275494,"journal":{"name":"2022 International Electron Devices Meeting (IEDM)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133532527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Energy-and Area-Efficient 8T SRAM Cell with FEOL CFETs and BEOL-Compatible Transistors 具有FEOL cfet和beol兼容晶体管的能量和面积高效8T SRAM单元
2022 International Electron Devices Meeting (IEDM) Pub Date : 2022-12-03 DOI: 10.1109/IEDM45625.2022.10019543
Ming Lee, Zi-Yuan Huang, Shaoyong Fan, Yu-Cheng Lu, V. Hu
{"title":"Energy-and Area-Efficient 8T SRAM Cell with FEOL CFETs and BEOL-Compatible Transistors","authors":"Ming Lee, Zi-Yuan Huang, Shaoyong Fan, Yu-Cheng Lu, V. Hu","doi":"10.1109/IEDM45625.2022.10019543","DOIUrl":"https://doi.org/10.1109/IEDM45625.2022.10019543","url":null,"abstract":"High energy efficiency and capacity embedded SRAMs are essential for data-centric applications. CFET is remarkably scalable and has been proven to maintain the SRAM scaling track compared to nanosheet (NS) FET. However, the 6T CFET SRAM still suffers the read/write conflict and requires assist-circuits. This paper proposed an optimized 8T CFET $_{mathrm {{BEOL}}}$ SRAM cell integrated with FEOL CFETs and BEOL-compatible transistors. Compared to the 6T NS SRAM, the optimized 8T CFET$_{mathrm {{BEOL}}}$ SRAM cell shows 40% cell area reduction, 2.2 times higher RSNM, 1.68 times larger WSNM, 53% reduction in cell read access time, 27.8% decrease in dynamic energy, and 65.7% improvements in energy-delay product. The proposed energy-and area-efficient 8T CFET$_{mathrm {{BEOL}}}$ SRAM with fast speed, low dynamic energy, and superior stability could be promising candidates for high throughput data-centric applications.","PeriodicalId":275494,"journal":{"name":"2022 International Electron Devices Meeting (IEDM)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132377439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Bacterial nanopores open the future of data storage 细菌纳米孔开启了数据存储的未来
2022 International Electron Devices Meeting (IEDM) Pub Date : 2022-12-03 DOI: 10.1109/IEDM45625.2022.10019421
Chan Cao, Lucien F. Krapp, Alissa Agerova, Abdelaziz Al Ouahabi, A. Radenović, Jean‐François Lutz, M. D. Peraro
{"title":"Bacterial nanopores open the future of data storage","authors":"Chan Cao, Lucien F. Krapp, Alissa Agerova, Abdelaziz Al Ouahabi, A. Radenović, Jean‐François Lutz, M. D. Peraro","doi":"10.1109/IEDM45625.2022.10019421","DOIUrl":"https://doi.org/10.1109/IEDM45625.2022.10019421","url":null,"abstract":"In the era of “big data” finding solutions for data storage alternative to those based on silicon or magnetic tapes is an urgent need for our society. The development of polymers that can store information at the molecular level has opened up new opportunities for ultrahigh density data storage, long-term archival, anti-counterfeiting systems and molecular cryptography. Biological pores of bacterial origin hold the promise to accurately decode the digital information encoded in tailored-made polymers opening up promising possibilities to develop writing-reading technologies to process digital data using a biological-inspired platform.","PeriodicalId":275494,"journal":{"name":"2022 International Electron Devices Meeting (IEDM)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121941024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Ab initio quantum transport simulations of defective devices based on 2-D materials via a projected-GW approach 基于投影gw方法的二维材料缺陷器件的从头算量子输运模拟
2022 International Electron Devices Meeting (IEDM) Pub Date : 2022-12-03 DOI: 10.1109/IEDM45625.2022.10019510
G. Gandus, J. Cao, T. Agarwal, M. Luisier, Y. Lee
{"title":"Ab initio quantum transport simulations of defective devices based on 2-D materials via a projected-GW approach","authors":"G. Gandus, J. Cao, T. Agarwal, M. Luisier, Y. Lee","doi":"10.1109/IEDM45625.2022.10019510","DOIUrl":"https://doi.org/10.1109/IEDM45625.2022.10019510","url":null,"abstract":"We propose a novel ab inito defect modeling framework for devices based on two-dimensional (2-D) transition-metal dichalcogenide (TMDC) monolayers. The so-called projected (p)- GW method is combined with density functional theory and incorporated into the non-equilibrium Green’s function equations to efficiently and accurately investigate the influence of various defect types on the characteristics of 2-D field-effect transistors. Through quasi-particle correlated defect-level modeling, we show that one single defect located inside the channel under the gate is a main source to block the current flow, thus leading to a large performance degradation. Our variability study also confirms that defects inside transistors based on 2-D TMDC monolayers induce a significant threshold voltage shift and ON-state current variation.","PeriodicalId":275494,"journal":{"name":"2022 International Electron Devices Meeting (IEDM)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123793851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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