Energy-and Area-Efficient 8T SRAM Cell with FEOL CFETs and BEOL-Compatible Transistors

Abstract

High energy efficiency and capacity embedded SRAMs are essential for data-centric applications. CFET is remarkably scalable and has been proven to maintain the SRAM scaling track compared to nanosheet (NS) FET. However, the 6T CFET SRAM still suffers the read/write conflict and requires assist-circuits. This paper proposed an optimized 8T CFET $_{\mathrm {{BEOL}}}$ SRAM cell integrated with FEOL CFETs and BEOL-compatible transistors. Compared to the 6T NS SRAM, the optimized 8T CFET$_{\mathrm {{BEOL}}}$ SRAM cell shows 40% cell area reduction, 2.2 times higher RSNM, 1.68 times larger WSNM, 53% reduction in cell read access time, 27.8% decrease in dynamic energy, and 65.7% improvements in energy-delay product. The proposed energy-and area-efficient 8T CFET$_{\mathrm {{BEOL}}}$ SRAM with fast speed, low dynamic energy, and superior stability could be promising candidates for high throughput data-centric applications.