A > 64 Multiple States and > 210 TOPS/W High Efficient Computing by Monolithic Si/CAAC-IGZO + Super-Lattice ZrO2/Al2 O3/ZrO2 for Ultra-Low Power Edge AI Application

Abstract

We present a novel Si/CAACFIGZO + SuperLattice ZrO2/Al2 O3/ZrO2 (SL-ZAZ) analog in-memory computing (AiMC) chip by monolithic 3D technique with the high thermal stability of Si/OS process. The SL-ZAZ not just improves storage capacitance > 50 %, but also makes leakage current lower > 30% compared with our last year’s IEDM work. Due to this study, the monolithic Si/CAAC-IGZO + SL-ZAZ technique can further reduce unit cell layout area by 25 % for ultra-low power edge A I application. This monolithic AiMC chip achieves > 64 multiple weighting states, an operation energy efficiency > 210 TOPS/W, and an inference accuracy can keep over 90 % (MNIST) even at 125°C high temperature operation.