M.-C. Chen, S. Ohshita, S. Amano, Y. Kurokawa, S. Watanabe, Y. Imoto, Y. Ando, Wen-Hsuang Hsieh, C.H. Chang, C. Wu, S. Chuang, H. Yoshida, M. Lu, M. Liao, S. Chang, S. Yamazaki
{"title":"单片Si/CAAC-IGZO +超晶格ZrO2/ al2o3 /ZrO2超低功耗边缘人工智能应用的A > 64多态和> 210 TOPS/W高效计算","authors":"M.-C. Chen, S. Ohshita, S. Amano, Y. Kurokawa, S. Watanabe, Y. Imoto, Y. Ando, Wen-Hsuang Hsieh, C.H. Chang, C. Wu, S. Chuang, H. Yoshida, M. Lu, M. Liao, S. Chang, S. Yamazaki","doi":"10.1109/IEDM45625.2022.10019324","DOIUrl":null,"url":null,"abstract":"We present a novel Si/CAACFIGZO + SuperLattice ZrO2/Al2 O3/ZrO2 (SL-ZAZ) analog in-memory computing (AiMC) chip by monolithic 3D technique with the high thermal stability of Si/OS process. The SL-ZAZ not just improves storage capacitance > 50 %, but also makes leakage current lower > 30% compared with our last year’s IEDM work. Due to this study, the monolithic Si/CAAC-IGZO + SL-ZAZ technique can further reduce unit cell layout area by 25 % for ultra-low power edge A I application. This monolithic AiMC chip achieves > 64 multiple weighting states, an operation energy efficiency > 210 TOPS/W, and an inference accuracy can keep over 90 % (MNIST) even at 125°C high temperature operation.","PeriodicalId":275494,"journal":{"name":"2022 International Electron Devices Meeting (IEDM)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A > 64 Multiple States and > 210 TOPS/W High Efficient Computing by Monolithic Si/CAAC-IGZO + Super-Lattice ZrO2/Al2 O3/ZrO2 for Ultra-Low Power Edge AI Application\",\"authors\":\"M.-C. Chen, S. Ohshita, S. Amano, Y. Kurokawa, S. Watanabe, Y. Imoto, Y. Ando, Wen-Hsuang Hsieh, C.H. Chang, C. Wu, S. Chuang, H. Yoshida, M. Lu, M. Liao, S. Chang, S. Yamazaki\",\"doi\":\"10.1109/IEDM45625.2022.10019324\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a novel Si/CAACFIGZO + SuperLattice ZrO2/Al2 O3/ZrO2 (SL-ZAZ) analog in-memory computing (AiMC) chip by monolithic 3D technique with the high thermal stability of Si/OS process. The SL-ZAZ not just improves storage capacitance > 50 %, but also makes leakage current lower > 30% compared with our last year’s IEDM work. Due to this study, the monolithic Si/CAAC-IGZO + SL-ZAZ technique can further reduce unit cell layout area by 25 % for ultra-low power edge A I application. This monolithic AiMC chip achieves > 64 multiple weighting states, an operation energy efficiency > 210 TOPS/W, and an inference accuracy can keep over 90 % (MNIST) even at 125°C high temperature operation.\",\"PeriodicalId\":275494,\"journal\":{\"name\":\"2022 International Electron Devices Meeting (IEDM)\",\"volume\":\"103 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-12-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 International Electron Devices Meeting (IEDM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM45625.2022.10019324\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 International Electron Devices Meeting (IEDM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM45625.2022.10019324","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A > 64 Multiple States and > 210 TOPS/W High Efficient Computing by Monolithic Si/CAAC-IGZO + Super-Lattice ZrO2/Al2 O3/ZrO2 for Ultra-Low Power Edge AI Application
We present a novel Si/CAACFIGZO + SuperLattice ZrO2/Al2 O3/ZrO2 (SL-ZAZ) analog in-memory computing (AiMC) chip by monolithic 3D technique with the high thermal stability of Si/OS process. The SL-ZAZ not just improves storage capacitance > 50 %, but also makes leakage current lower > 30% compared with our last year’s IEDM work. Due to this study, the monolithic Si/CAAC-IGZO + SL-ZAZ technique can further reduce unit cell layout area by 25 % for ultra-low power edge A I application. This monolithic AiMC chip achieves > 64 multiple weighting states, an operation energy efficiency > 210 TOPS/W, and an inference accuracy can keep over 90 % (MNIST) even at 125°C high temperature operation.
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