{"title":"Extraction of the trap density at the gate periphery using the gated diode array for giga-bit DRAMs","authors":"H. Suzuki, M. Kojima, Y. Nara","doi":"10.1109/ICMTS.1999.766228","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766228","url":null,"abstract":"Gated diode arrays which have varied peripheral length around the gates are proposed to evaluate the leakage current at the gate periphery of deep sub-micron devices. Due to the high electric field at the gate edge in deep sub-micron devices, the leakage current is enhanced by trap-assisted tunneling. The leakage currents at the gate edge were measured independently of the junction bias voltage with the gated diode arrays. This allows extraction of the trap density at the gate edge, even for deep sub-micron devices with high doping concentration. This method is useful for extraction of the trap density at the gate edge, which is the key parameter for control of the junction leakage current, for deep sub-micron devices in giga-bit DRAM.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121711054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Measurement of V/sub T/ and L/sub eff/ using MOSFET gate-substrate capacitance","authors":"M. Lau, C. Chiang, Y. Yeow, Z. Yao","doi":"10.1109/ICMTS.1999.766234","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766234","url":null,"abstract":"This paper describes and demonstrates new methods for the measurement of MOSFET threshold voltage and effective channel length using gate-to-substrate capacitance C/sub gb/. The measurement does not require DC drain current flowing between drain and source and thus eliminate the effect of source and drain resistances and the presence of an asymmetric potential profile between source and drain.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123022102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A simple physical extraction method for R/sub D/-R/sub S/ of asymmetric MOSFETs","authors":"Alfred Blaum, James Victory, Colin C. McAndrewt","doi":"10.1109/ICMTS.1999.766232","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766232","url":null,"abstract":"MOSFETs with different drain and source series resistance, R/sub D/ and R/sub S/, are common both in medium and high power technologies and in deep submicron technologies. Proper modeling of asymmetric MOSFETs requires accurate characterization of R/sub D/-R/sub S/. This paper presents the concept and the results of a new, simple, and physical extraction technique to determine R/sub D/-R/sub S/ purely based on experimental data. The method makes minimal assumptions about MOSFET drain current modeling.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130250726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The impact of noise parameter de-embedding on the high-frequency noise modeling of MOSFETs","authors":"M. Deen, Chih-Hung Chen","doi":"10.1109/ICMTS.1999.766212","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766212","url":null,"abstract":"This paper discusses the impact of noise parameter de-embedding in n-MOSFETs. A method to directly de-embed the parasitic pad effects from the measured noise parameters (minimum noise figure NF/sub min/, equivalent noise resistance R/sub n/, and optimized source reflection coefficient /spl Gamma//sub opt/) and the impact of noise parameter de-embedding on the high-frequency noise modeling of MOSFETs is presented. In addition, noise parameter de-embedding using a physically-based pad model is presented. Finally, the results of the two approaches are compared.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"218 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128624819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A new test structure for direct extraction of SPICE model parameters for double polysilicon bipolar transistors","authors":"M. Sandén, Shi-Li Zhang, J. Grahn, M. Ostling","doi":"10.1109/ICMTS.1999.766211","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766211","url":null,"abstract":"Direct extraction of ten core SPICE model parameters for double polysilicon bipolar junction transistors (BJTs) was performed using a new test structure. The test structure was basically identical to a real BJT, but without the intrinsic base. Hence, the extrinsic parasitics of the test structure were identical to the BJT. From the test structure small-signal model, all extrinsic model parameters were directly extracted from the measured scattering parameters over the frequency range of 1 to 18 GHz. The values of the extracted parameters were in good agreement compared to those obtained using other conventional methods.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115681211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Identification of plasma induced damage conditions in VLSI designs","authors":"P. Simon, Wojciech Maly","doi":"10.1109/ICMTS.1999.766206","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766206","url":null,"abstract":"Typically, the plasma charging effect is investigated by using antenna test structures that do not replicate conditions occurring in real VLSI ICs well enough. Consequently, understanding, modelling and detection of plasma charging induced gate oxide damage in real ICs is often inadequate. This paper discusses a new plasma charging monitoring technique that assesses the extent of this problem. This technique employs a multiplexed antenna monitoring (MAM) test structure with more than 400 antenna configurations in order to determine the dependency between IC layout and the extent of gate oxide damage. The paper reports the results of application of this technique to a 0.35 /spl mu/m, 75 /spl Aring/ gate oxide CMOS technology. The obtained results lead to a new definition of \"antenna ratio\" which is proposed to capture plasma charging conditions in real VLSI devices.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127118769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Smith, I. Lindsay, A. Walton, M. Cresswell, L. W. Linholm, R. Allen, M. Fallon, A. Gundlach
{"title":"Analysis of current flow in mono-crystalline electrical linewidth structures","authors":"S. Smith, I. Lindsay, A. Walton, M. Cresswell, L. W. Linholm, R. Allen, M. Fallon, A. Gundlach","doi":"10.1109/ICMTS.1999.766207","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766207","url":null,"abstract":"The current flow in lightly doped mono-crystalline silicon structures designed for use as low cost secondary reference linewidth standards is investigated. It is demonstrated that surface charge can have a significant effect upon the measurements of linewidth test structures. The effect of surface charge on <110> Greek cross structures is also investigated and the influence of a gate electrode on the extracted value of sheet resistance demonstrated. It is confirmed that the resulting uncertainty in both of these measurements can be simply overcome by degenerately doping the silicon during the fabrication process.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114779859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S.A. AbuGhazeleh, P. Christie, V. Agrawal, J. Stevenson, A. Walton, A. Gundlach, S. Smith
{"title":"Null holographic test structures for the measurement of overlay and its statistical variation","authors":"S.A. AbuGhazeleh, P. Christie, V. Agrawal, J. Stevenson, A. Walton, A. Gundlach, S. Smith","doi":"10.1109/ICMTS.1999.766235","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766235","url":null,"abstract":"Results are presented on the use of null wire segment holograms for the in-line assessment of mask alignment errors in the chip fabrication process. Process variations are detected by measuring the light intensity generated by a hologram designed to project a null image. To detect alignment errors, the mask for the wire segment hologram is distributed between two mask layers. If the two sets of diffracting structures defined by the masks are transferred to the wafer with perfect registration, the result is an area of light cancellation (null) in the image plane. Increased mask misalignment leads to imperfect wavefront cancellation which is manifested as an increase in light intensity in the null region. In order to characterize misalignment under controlled conditions, the two portions of the holographic test structure were initially recombined into a single structure but with intentional misalignment between the two portions designed into the mask. The technique was then used to characterize the alignment errors between two separate masks, with the actual fabricated offsets measured by atomic force microscopy. Initial results indicate the technique is capable of resolving 0.1 /spl mu/m mask misalignment for a 1 /spl mu/m minimum feature process.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125789369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Contribution to the characterization of the hump effect in MOSFET submicronic technologies","authors":"H. Brut, R. Velghe","doi":"10.1109/ICMTS.1999.766241","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766241","url":null,"abstract":"A new method allowing the automatic characterization of the subthreshold hump effect (Sallagoity et al., IEEE TED vol. 43, no. 11, pp. 1900-6, 1996) is presented in this paper. It makes use of a variable transformation based on observations made with a hump model. This model considers two sub-transistors with different threshold voltages in parallel. The extracted parameters are the hump effect magnitude, the weak inversion slope and the extrapolated leakage current at V/sub g/=0 V. After implementation in our automatic test system, the routine has been successfully applied to the 0.25 /spl mu/m technology of the Crolles Centre Commun. The efficiency and reliability of this routine are demonstrated whatever the operating bias and temperature. It is noticed that this method is a useful tool to monitor and study the hump effect.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115792718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Identification of MOS oxide defect location with a spatial resolution less than 0.1 /spl mu/m using photoemission microscope","authors":"T. Ohzone, M. Yuzaki, T. Matsuda, E. Kameda","doi":"10.1109/ICMTS.1999.766222","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766222","url":null,"abstract":"The maximum photoemission position corresponding to an oxide defect was determined with a spatial resolution of less than 0.1 /spl mu/m by a combination of an improved photoemission microscope with a magnification of 500/spl times/ and a MOS capacitor test structure which had a periodic X-Y matrix pattern to define the precise oxide-defect location. The field-oxide islands, which had photoemission spots from the oxide defects, were distributed at random. The LOCOS edge corresponding to the intensity dent of the reflected light image was located at about +0.3 /spl mu/m from the gate-oxide edge. The oxide defects were located in a range from +0.4/spl sim/-0.1 /spl mu/m from the LOCOS edge.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126770390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}