Extraction of the trap density at the gate periphery using the gated diode array for giga-bit DRAMs

Abstract

Gated diode arrays which have varied peripheral length around the gates are proposed to evaluate the leakage current at the gate periphery of deep sub-micron devices. Due to the high electric field at the gate edge in deep sub-micron devices, the leakage current is enhanced by trap-assisted tunneling. The leakage currents at the gate edge were measured independently of the junction bias voltage with the gated diode arrays. This allows extraction of the trap density at the gate edge, even for deep sub-micron devices with high doping concentration. This method is useful for extraction of the trap density at the gate edge, which is the key parameter for control of the junction leakage current, for deep sub-micron devices in giga-bit DRAM.