ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)最新文献

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An investigation of on-chip spiral inductors on a 0.6 /spl mu/m BiCMOS technology for RF applications 射频应用中0.6 /spl μ m BiCMOS技术片上螺旋电感的研究
J. A. Power, S. C. Kelly, E. Griffith, M. O’Neill
{"title":"An investigation of on-chip spiral inductors on a 0.6 /spl mu/m BiCMOS technology for RF applications","authors":"J. A. Power, S. C. Kelly, E. Griffith, M. O’Neill","doi":"10.1109/ICMTS.1999.766209","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766209","url":null,"abstract":"Inductors are very important passive elements in many RF circuit applications. Integrated on-chip metal inductors, formed in conventional CMOS or BiCMOS technologies, suffer from performance limitations due to substrate injection through the oxide, metal resistive losses, and substrate losses due to low-resistivity substrates. These problems mean that the highest attainable inductor quality factor (Q) is significantly lower than that which can be attained from off-chip inductors. This paper details an analysis of on-chip metal inductors fabricated on a 0.6 /spl mu/m BiCMOS technology. Issues relating to test structure layout, measurement techniques, inductor composition, and inductor characterization and modeling are addressed. In addition, an analysis of the impact of inductor shape and metal thickness on inductor performance is examined.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126580576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Simple technique for the measurement of thermal time constants of microbolometer structures 测量微测热计结构热时间常数的简单技术
P. Lambkin, N. Folan, B. Lane
{"title":"Simple technique for the measurement of thermal time constants of microbolometer structures","authors":"P. Lambkin, N. Folan, B. Lane","doi":"10.1109/ICMTS.1999.766239","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766239","url":null,"abstract":"A straightforward electrical technique for determining the thermal time constant of microbolometer structures is presented. An impedance measurement of a microbolometer using an LCR meter shows that the phase lag/lead reaches a maximum as a function of frequency. It is shown that the frequency of maximum phase difference is simply related to the thermal time constant.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127754804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A high density matched hexagonal transistor structure in standard CMOS technology for high speed applications 高密度匹配六角形晶体管结构在标准CMOS技术高速应用
A. van den Bosch, M. Steyaert, W. Sansen
{"title":"A high density matched hexagonal transistor structure in standard CMOS technology for high speed applications","authors":"A. van den Bosch, M. Steyaert, W. Sansen","doi":"10.1109/ICMTS.1999.766245","DOIUrl":"https://doi.org/10.1109/ICMTS.1999.766245","url":null,"abstract":"In this paper, a very dense CMOS hexagonal transistor structure is presented. The main advantages of the transistors are the low parasitic drain and source capacitance due to the small area. The matching properties of this structure have been investigated and these results have been compared to those for traditional finger style structures. Exploiting these advantages, these transistors are very well suited for high speed applications with a demand for both good matching and small area, such as e.g. multi-bit current steering D/A converters. The test chips have been implemented in a standard 0.5 /spl mu/m CMOS technology. No adaptations to the technology have been made in order to realize the structures.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122409205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
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