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1991, Proceedings. International Test Conference最新文献

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Arbitrary Waveform Generation with Absolute Duration Control 任意波形生成与绝对持续时间控制
1991, Proceedings. International Test Conference Pub Date : 1991-10-26 DOI: 10.1109/TEST.1991.519704
B. J. Dinteman
{"title":"Arbitrary Waveform Generation with Absolute Duration Control","authors":"B. J. Dinteman","doi":"10.1109/TEST.1991.519704","DOIUrl":"https://doi.org/10.1109/TEST.1991.519704","url":null,"abstract":"In Arbitrary Waveform Generator applications, “segmented” packets produce diverse waveforms. Anew architecture varies segment duration by varying the data rate. At the AWG’s 16 GHz effectiveclockrate, waveformresolution far surpasses conventional AWGs.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115946372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Cube-Contained Random Patterns and their Application to the Complete Testing of Synthesized Multi-le 包含立方体的随机模式及其在合成多态完全测试中的应用
1991, Proceedings. International Test Conference Pub Date : 1991-10-26 DOI: 10.1109/TEST.1991.519709
S. Pateras, J. Rajski
{"title":"Cube-Contained Random Patterns and their Application to the Complete Testing of Synthesized Multi-le","authors":"S. Pateras, J. Rajski","doi":"10.1109/TEST.1991.519709","DOIUrl":"https://doi.org/10.1109/TEST.1991.519709","url":null,"abstract":"The novel concept of cube-contained random patterns represents an alternative to weighted random pattern testing. Reductions in random pattern test lengths are achieved by the successive assignment of temporarily fixed values to selected inputs during the random pattern generation process. Experimental results show that cube-contained random patterns can achieve 100% fault coverage of synthesized ciscuits using orders of magnitude less patterns than when equiprobable random patterns are used.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116615197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
A Computer Architecture for High Pin Count Testers 高引脚数测试仪的计算机体系结构
1991, Proceedings. International Test Conference Pub Date : 1991-10-26 DOI: 10.1109/TEST.1991.519772
Chris Hannaford
{"title":"A Computer Architecture for High Pin Count Testers","authors":"Chris Hannaford","doi":"10.1109/TEST.1991.519772","DOIUrl":"https://doi.org/10.1109/TEST.1991.519772","url":null,"abstract":"A unique architectural feature of a new mixed signal tester is its processor per pin computer architecture. The system requirements that dictated the use of such an architecture are described. The hardware implementation is detailed, and the resultant system performance is examined. The use of the per pin processor for implementing novel functions is described.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123369079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
HIGH PERFORMANCE PIN ELECTRONICS EMPLOYING GaAs IC AND HYBRID CIRCUIT PACKAGING TECHNOLOGY 采用GaAs集成电路和混合电路封装技术的高性能引脚电子器件
1991, Proceedings. International Test Conference Pub Date : 1991-10-26 DOI: 10.1109/TEST.1991.519743
B. Baril, D. Clayson, D. McCracken, S. Taylor
{"title":"HIGH PERFORMANCE PIN ELECTRONICS EMPLOYING GaAs IC AND HYBRID CIRCUIT PACKAGING TECHNOLOGY","authors":"B. Baril, D. Clayson, D. McCracken, S. Taylor","doi":"10.1109/TEST.1991.519743","DOIUrl":"https://doi.org/10.1109/TEST.1991.519743","url":null,"abstract":"This paper describes the latest generation of pin electronics developed for a high-speed verification ATE system. The pin electronics sub-system provides a driverireceiver with outstanding bandwidth in addition to per-pin current loading and per-pin parametrics. A f.11 custom GaAs IC provides the major features and advanced performance of the driver, receiver, and current load. The combined modules use only 2.5 square inches of circuit board area per tester channel. This paper details the circuit design and measured perfor,mance of the GaAs IC and the three hybrid multichip rzwdules that complete the pin electronics Bnctions.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122357281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
AN EFFICIENT, FORWARD FAULT SIMULATION ALGORITHM BASED ON THE PARALLEL PATTERN SINGLE FAULT PROPAGAT 一种基于并行模式单故障传播的高效前向故障仿真算法
1991, Proceedings. International Test Conference Pub Date : 1991-10-26 DOI: 10.1109/TEST.1991.519760
H. K. Lee, D. Ha
{"title":"AN EFFICIENT, FORWARD FAULT SIMULATION ALGORITHM BASED ON THE PARALLEL PATTERN SINGLE FAULT PROPAGAT","authors":"H. K. Lee, D. Ha","doi":"10.1109/TEST.1991.519760","DOIUrl":"https://doi.org/10.1109/TEST.1991.519760","url":null,"abstract":"In this paper, we present a fast fault simulator, FSIM, for combinational circuits. FSIM is based on the parallel pattern single fault propagation (PPSFP) technique. The essential idea of FSIM is to simulate the circuit in the forward levelized order and to prune off unnecessary gates in the early stages. In this way, FSIM performs fault simulations only for the gates which are affected by 'the injected faults. Another key feature employed in FSIM is the use of multiple last-in first-out (L,IFO) stacks instead of the commonly used priority queue [9]. The propagation time of the mult,iple LIFO stacks is O(n) and that of the priority queue O(n log n), where n is the number of gates in the propagation zone of the fault under consideration. The two features achieve a substantial reduction of the processing time. Experimental results for ten benchmark circuits show that FSIM outperforms other competing PPSFP fault simulators, Moreover, the efficiency of FSIM is less dependent on the circuit structure than other fault simulators. Experimental results of FSIM for various packet sizes, i.e., the number of test patterns simulated at a time, are also presented.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121147038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 179
SEARCH STATE EQUIVALENCE FOR REDUNDANCY IDENTIFICATION AND TEST GENERATION 搜索状态等价，进行冗余识别和测试生成
1991, Proceedings. International Test Conference Pub Date : 1991-10-26 DOI: 10.1109/TEST.1991.519509
J. Giraldi, M. Bushnell
{"title":"SEARCH STATE EQUIVALENCE FOR REDUNDANCY IDENTIFICATION AND TEST GENERATION","authors":"J. Giraldi, M. Bushnell","doi":"10.1109/TEST.1991.519509","DOIUrl":"https://doi.org/10.1109/TEST.1991.519509","url":null,"abstract":"We present new extensions to the EST' algoritlm, which accelerates combinational circuit Redundancy Identification and Automatic Test Pattern Generation (ATPG) algorithms, in particular SOCRATES. EST detects equivalent search states, which are saved. for all faults during ATPG. The search space is reduced by using learned Search State equiualences to detect previously-encountered search states (possibly from prior faults) and to make internal node assignments. We present two extensions to EST. The first ensures that each portion of the ATPG search space is explored only once. The second applies headline objectives in parallel, rather than serially. For the 1965 ISCAS combinational benchmarks, EST accelerates S 0 CRATES by 6.53 times, when all faults are targeted, and by 5.51 times, when used with random pattern generation, f,iult simulation and fault dropping. This acceleration was achieved with minimal memory overhead.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127559143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
Integrating Emulation Techniques Into General Purpose ATE 将仿真技术集成到通用ATE中
1991, Proceedings. International Test Conference Pub Date : 1991-10-26 DOI: 10.1109/TEST.1991.519766
R. W. Williams
{"title":"Integrating Emulation Techniques Into General Purpose ATE","authors":"R. W. Williams","doi":"10.1109/TEST.1991.519766","DOIUrl":"https://doi.org/10.1109/TEST.1991.519766","url":null,"abstract":"Testers basedon emulation techniques are not new. They typically use a hardware “Pod” to intercept thecontrol signals from themicroprocessor, allowing theemulation testertcu takecontrolofthemicroprocessorbus. This paper shows howageneralpurpose ATE with clock synchronization and triggering capability can take control of the microprocessor bus using special software, SoftPodTM, rather than special hardware pods This enables the test engineer to use an emulation strategy to develop tests.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126028609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Parity Bit Calculation and Test Signal Compaction for BTST Applications BTST应用的奇偶校验位计算和测试信号压缩
1991, Proceedings. International Test Conference Pub Date : 1991-10-26 DOI: 10.1109/TEST.1991.519769
Sungju Park, S. Akers
{"title":"Parity Bit Calculation and Test Signal Compaction for BTST Applications","authors":"Sungju Park, S. Akers","doi":"10.1109/TEST.1991.519769","DOIUrl":"https://doi.org/10.1109/TEST.1991.519769","url":null,"abstract":"Parity bit checking and pseudo-exhaustive testing are two design techniques which have been widely discussed in the BIST literature but have seldom been employed in practice because of the exponential nature of the processes involved. In this paper we describe several procedures designed to avoid these exponential explosions. Specifically we show how the parity of a large combinational function can (often) be quickly calculated. This is accomplished by an examination of the circuit realization itself particularly with regard to the connectivity between the various inputs and outputs. We then show how this same approach can be used to partition circuits so that they can be tested efficiently with a relatively small number of test patterns. Using these methods we were able to calculate the parity bits for more than 80% of ISCAS benchmark circuits' outputs. Interestingly enough, only 15% of these outputs were found to be parity-odd, but for these cases high fault coverage was invariably found to result. Several examples are included.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114671679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fast sequential ATPG based on implicit state enumeration 基于隐式状态枚举的快速顺序ATPG
1991, Proceedings. International Test Conference Pub Date : 1991-10-26 DOI: 10.1109/TEST.1991.519495
Hyunwoo Cho, G. Hachtel, F. Somenzi
{"title":"Fast sequential ATPG based on implicit state enumeration","authors":"Hyunwoo Cho, G. Hachtel, F. Somenzi","doi":"10.1109/TEST.1991.519495","DOIUrl":"https://doi.org/10.1109/TEST.1991.519495","url":null,"abstract":"The knowledge of the State Transition Graph (STG) of a sequential circuit helps in generating test sequences. For instance, by determining that a set of states is not reachable from the reset state, it is possible to identify a certain type of sequentially untestable faults. However, until recently, the ability of algorithms to store the STG of a sequential circuit has been limited to small instances. Recent advances in sequential circuit verification, based on the use of binary decision diagrams and new powerful implicit enumeration algorithms, have dramatically improved our ability to deal with large numbers of states. In this paper we report on the application of these algorithms to the problems of generating justification sequences, identifying redundancies, and dealing with hard-to-detect faults. Our experiments show substantial improvements over previously published results.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124178658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 58
A Product Information Access System for the Verification, Test, Diagnosis and Repair of Electronic A 一种用于电子产品验证、测试、诊断和维修的产品信息访问系统
1991, Proceedings. International Test Conference Pub Date : 1991-10-26 DOI: 10.1109/TEST.1991.519524
J. McWha, Peter Kouklamanis
{"title":"A Product Information Access System for the Verification, Test, Diagnosis and Repair of Electronic A","authors":"J. McWha, Peter Kouklamanis","doi":"10.1109/TEST.1991.519524","DOIUrl":"https://doi.org/10.1109/TEST.1991.519524","url":null,"abstract":"manual probing of modules. his paper will discuss the principles, requirements, and advantages of the Product Infcirmation A~~~~ system (PIAS). ms system aids ,the llSer with verification, test, diagnosis and repair of electronic assemblies (modules) in a tightly integrated workstation-based environment. PIAS utilizes a distributed relational database that contains design, test, and diagnostic data. It consists of unit assembly and circuit schematic displays, a physical to logical data cross referencer, and a base:","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"358 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125646084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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