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1991, Proceedings. International Test Conference最新文献

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DELAY TESTING OF DIGITAL CIRCUITS BY OUTPUT WAVEFORM ANALYSIS 通过输出波形分析测试数字电路的延迟
1991, Proceedings. International Test Conference Pub Date : 1991-10-26 DOI: 10.1109/TEST.1991.519745
P. Franco, E. McCluskey
{"title":"DELAY TESTING OF DIGITAL CIRCUITS BY OUTPUT WAVEFORM ANALYSIS","authors":"P. Franco, E. McCluskey","doi":"10.1109/TEST.1991.519745","DOIUrl":"https://doi.org/10.1109/TEST.1991.519745","url":null,"abstract":"A new method for delay fault testing of digital circuits is presented. Unlike catastrophic failures that simply have incorrect steady-state logic values at the circuit outputs, delay faults change the shape of the output waveforms by moving the signal transitions in time. Therefore, since the output waveforms contain information about the circuit delays, instead of only latching the outputs at the sampling time, the output waveforms between samples are analyzed as well. Two classes of output waveform analysis are discussed. In the first technique, the output waveform is observed for any changes after the sampling time, since in a fault-free circuit, the outputs are expected to have stabilized at the desired logic values. In the second technique, information is extracted from the faulty and fault-free waveforms before the sampling time, and compared for any differences. Circuits for the waveform analyzers are presented to show that the method is feasible, and experimental results are given.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133059315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 73
ARTEST: AN ARCHITECTURAL LEVEL TEST GENERATOR FOR DATA PATH FAULTS AND CONTROL FAULTS Artest:用于数据路径故障和控制故障的架构级测试生成器
1991, Proceedings. International Test Conference Pub Date : 1991-10-26 DOI: 10.1109/TEST.1991.519738
Jaushin Lee, J. Patel
{"title":"ARTEST: AN ARCHITECTURAL LEVEL TEST GENERATOR FOR DATA PATH FAULTS AND CONTROL FAULTS","authors":"Jaushin Lee, J. Patel","doi":"10.1109/TEST.1991.519738","DOIUrl":"https://doi.org/10.1109/TEST.1991.519738","url":null,"abstract":"In this paper, an ATF’G methodology working at an architectural level is proposed. For the data path portion, the hierarchy of the design is exploited and the dependence on the gate level information is relieved. For the conb’oi faults, gate level algorithms are incorporated with high level approaches to excite the fault and differentiate the fault effect to primary outputs. Due to the fault collapsing effect arid the fault differentiation process, several data types have been defined for the manipulation alf all possible fault e€fects. A functional equivalent model is used for sequential modules, which makes this technique extendable beyond the register-transfer level. The backtracking mechanism used in the control unit has been carefully modified to ensure a complete finite space searching. Some experimerrtal results are presented to show the effectiveness of this approach.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131182738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
Multi-Step Stress Test for Yield Improvement of 16Mbit EPROMs with Redundancy Scheme 采用冗余方案提高16Mbit eprom成成率的多步应力测试
1991, Proceedings. International Test Conference Pub Date : 1991-10-26 DOI: 10.1109/TEST.1991.519716
J. Miyamoto, N. Ohtsuka, K. Imamiya, N. Tomita, Y. Iyama
{"title":"Multi-Step Stress Test for Yield Improvement of 16Mbit EPROMs with Redundancy Scheme","authors":"J. Miyamoto, N. Ohtsuka, K. Imamiya, N. Tomita, Y. Iyama","doi":"10.1109/TEST.1991.519716","DOIUrl":"https://doi.org/10.1109/TEST.1991.519716","url":null,"abstract":"To reject defective cells and to guarantee device reliability in a short time, internal test circuits have been implemented in non-volatile memories. On the other hand, for high density EPROMs, implementing column redundancy scheme is of vital importance in order to obtain a reasonable yield, as inter-connection design rules are limiting the cell size. However, the conventional column redundancy scheme was not very efficient, because the test circuits did not work well for one of the most dominant failures on miniaturized cells. This paper proposes a new test algorithm, multi-step stress test to solve the problem. The concept has been applied to an actual 16Mbit EPROM, and the yield has been improved to almost double that at the time of the initial developing stage.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130860147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The enVision Timing Resolver enVision定时解析器
1991, Proceedings. International Test Conference Pub Date : 1991-10-26 DOI: 10.1109/TEST.1991.519767
D. Organ
{"title":"The enVision Timing Resolver","authors":"D. Organ","doi":"10.1109/TEST.1991.519767","DOIUrl":"https://doi.org/10.1109/TEST.1991.519767","url":null,"abstract":"In device-oriented testing, the test program is created in terms of the device's data sheet. Timing diagrams are utilized. This paper examines some ambiguities and redundancies in timing diagrams found in data sheets with regard to automatic test generation. Their resolution is described in a partices is obvious. There are two cases where it becomes more difficult. First, some timing parameters may have both a minimum and a maximum value specified. The question is when to use which? Normally the solution is to use two-pass testing. The second situation is more difficult. There may be edges which must Conform to Several timing relaular device-oriented visual programming language.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115699796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
CURRENT VS. LOGIC TESTING OF GATE OXIDE SHORT, FLOATING GATE AND BRIDGING FAILURES IN CMOS cmos中栅极氧化物短路、浮栅和桥接故障的电流与逻辑测试
1991, Proceedings. International Test Conference Pub Date : 1991-10-26 DOI: 10.1109/TEST.1991.519713
R. Rodríguez-Montañés, J. Segura, V. Champac, J. Figueras, J. A. Rubio
{"title":"CURRENT VS. LOGIC TESTING OF GATE OXIDE SHORT, FLOATING GATE AND BRIDGING FAILURES IN CMOS","authors":"R. Rodríguez-Montañés, J. Segura, V. Champac, J. Figueras, J. A. Rubio","doi":"10.1109/TEST.1991.519713","DOIUrl":"https://doi.org/10.1109/TEST.1991.519713","url":null,"abstract":"Logic testing has s o m e well known l imi ta t ions f o r circuits with failures causing intermediate voltage levels or, even , correct logic outputs with parametric deuiat ions f r o m the fault free specificattons. For these failures current testing might be considered as a complementary technique t o logic testing. I n this work, these physical defects widely encountered i n ioday’s CMOS processes, are modelled taking into account t h e topology o f the defective circuit and the parameters o f the technology used. These models are used to simulate a t electrical level (SPICE) the behaviour of a simple three inver ter chain wi th a f au l t y inverter. T h e merits o f current testing in f ront of voltage testing are studied for the classes of defects modelled.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114582005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 101
ON TEST GENERATION FOR I/sub DDQ/ TESTING OF BRIDGING FAULTS IN CMOS CIRCUITS CMOS电路中I/sub DDQ/桥接故障测试的测试生成
1991, Proceedings. International Test Conference Pub Date : 1991-10-26 DOI: 10.1109/TEST.1991.519723
S. Bollinger, S. Midkiff
{"title":"ON TEST GENERATION FOR I/sub DDQ/ TESTING OF BRIDGING FAULTS IN CMOS CIRCUITS","authors":"S. Bollinger, S. Midkiff","doi":"10.1109/TEST.1991.519723","DOIUrl":"https://doi.org/10.1109/TEST.1991.519723","url":null,"abstract":"This paper describes a test generation methodology that supports explicit IDDe test generation for unrestricted bridging faults in CMOS circuits. A modular, hierarchical approach is used to accurately represent the structure of CMOS design styles and manage complexity. Performance results are presented for a preliminary implementation of the approach.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115599559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
ON THE INTEGRATION OF DESIGN AND MANUFACTURING FOR IMPROVED TESTABILITY 设计与制造一体化以提高可测试性
1991, Proceedings. International Test Conference Pub Date : 1991-10-26 DOI: 10.1109/TEST.1991.519516
R. Makki, K. Daneshvar, F. Tranjan, Richard Greene
{"title":"ON THE INTEGRATION OF DESIGN AND MANUFACTURING FOR IMPROVED TESTABILITY","authors":"R. Makki, K. Daneshvar, F. Tranjan, Richard Greene","doi":"10.1109/TEST.1991.519516","DOIUrl":"https://doi.org/10.1109/TEST.1991.519516","url":null,"abstract":"We present a new Manufacturing-For-Test technology based on new physical methods of testing digital VLSIIULSI circuits for faults, which has the potential for much greater testing efjciency than possible by conventional electrical addressing through external pins alone. The method uses variants of the pulsed laser probing of microelectronic devices, and various holographic techniques of formation of virtual (transient) interconnects, together with electrical pulse testing, to greatly increase test coverage. Combined with a Design-for-Test scheme, the new technology can significantly improve fault coverage by allowing direct access to internal nodes. The new Manufacturing-For-Test method utilizes standard fabrication technologies and introduces only a small area overhead, and circuit loading; it has the promise of low cost in manufacture and test, and requires no significant increase in the number of physical chip connections.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"178 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115410225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IMPLEMENTING BOUNDARY-SCAN AND PSEUDO-RANDOM BIST IN AN ASYNCHRONOUS TRANSFER MODE SWITCH 在异步传输模式切换中实现边界扫描和伪随机bist
1991, Proceedings. International Test Conference Pub Date : 1991-10-26 DOI: 10.1109/TEST.1991.519503
P. Thorel, J. Rainard, A. Botta, A. Chemarin, J. Majos
{"title":"IMPLEMENTING BOUNDARY-SCAN AND PSEUDO-RANDOM BIST IN AN ASYNCHRONOUS TRANSFER MODE SWITCH","authors":"P. Thorel, J. Rainard, A. Botta, A. Chemarin, J. Majos","doi":"10.1109/TEST.1991.519503","DOIUrl":"https://doi.org/10.1109/TEST.1991.519503","url":null,"abstract":"&pact : This paper shows how the features of both Boundary-Scan and Pseudo-Random BIST (Built-In Self Test) approaches go well together, implemented on a VLSI circuit devoted to telecommunications. The chosen circuit is a 0.7 p CMOS Asynchronous Transfer Mode (ATAI) switch of 350,000 transistors, for use in a 16 x 16 ATM Switching Matrix able to run at a throughpuu rate of up to 1.244 Gbitls. First, the nominal circuit is presented. Then the test approaches used are evoked, before discussing the main test problems encountered. The paper concludes with concrete results, validating tk chosen approaches and their applications in such a large circuit.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"18 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114135689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
COMPACTEST: A METHOD TO GENERATE COMPACT TEST SETS FOR COMBINATIONAL CIRCUITS Compactest:为组合电路生成紧凑测试集的方法
1991, Proceedings. International Test Conference Pub Date : 1991-10-26 DOI: 10.1109/TEST.1991.519510
I. Pomeranz, L. Reddy, S. Reddy
{"title":"COMPACTEST: A METHOD TO GENERATE COMPACT TEST SETS FOR COMBINATIONAL CIRCUITS","authors":"I. Pomeranz, L. Reddy, S. Reddy","doi":"10.1109/TEST.1991.519510","DOIUrl":"https://doi.org/10.1109/TEST.1991.519510","url":null,"abstract":"Heuristics to aid the derivation of small test sets that detect single stuck-at faults in combinational logic circuits are proposed. The heuristics can be added to existing test pattern generators without compromising fault coverage. Experimental results obtained by adding the proposed heuristics to a simple PODEM procedure and applying it to the ISCAS-85 and fully-scanned ISCAS-89 benchmark circuits are presented to substantiate the effectiveness of the proposed heuristics. >","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121601049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 434
LINEAR ERROR MODELING OF ANALOG AND MIXED-SIGNAL DEVICES 模拟和混合信号器件的线性误差建模
1991, Proceedings. International Test Conference Pub Date : 1991-10-26 DOI: 10.1109/TEST.1991.519720
G. Stenbakken, T., Michael Souders
{"title":"LINEAR ERROR MODELING OF ANALOG AND MIXED-SIGNAL DEVICES","authors":"G. Stenbakken, T., Michael Souders","doi":"10.1109/TEST.1991.519720","DOIUrl":"https://doi.org/10.1109/TEST.1991.519720","url":null,"abstract":"Techniquesare presented for developinglinear error models for analog and mixed-signal devices. Methods for choosingparameters and assuring the models are complete and wellconditioned, are included. Once established, the models can be used in a comprehensive approach for optimizing the testing of the subject devices.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121934910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
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